Audio digital-to-analog converter with enhanced dynamic range

Patent metadata

Field	Value
Publication number	US-2018145697-A1
Application number	US-201715821534-A
Country	US
Kind code	A1
Filing date	Nov 22, 2017
Priority date	Nov 22, 2016
Publication date	May 24, 2018
Grant date	—

Abstract

An audio digital-to-analog converter (DAC) achieves high dynamic range with low power consumption using a segmented DAC, also referred to as a noise shaped splitter. The noise shaped splitter is dynamically reconfigured based on envelope detection that tracks the amplitude of an n-bit digital input signal to the segmented DAC. The amplitude of the n-bit digital input signal can be expressed as the magnitude of a numerical value corresponding to the n bits of the digital signal. Based on the amplitude of the digital input signal, certain segments of the segmented DAC are bypassed and the components of each bypassed segment are turned off, saving power and reducing noise, and achieving improved dynamic range along with lower power consumption.

First claim

What is claimed is:

1 . A digital-to-analog conversion system comprising:
a data splitter operable to split a digital input signal into a plurality of data segments, wherein the digital input signal is expressed as a combination of the plurality of data segments; a plurality of signal paths, each of the plurality of signal paths having a plurality of processing elements operable to receive and process a corresponding one of the plurality of data segments; and a configuration controller operable to determine a subset of the plurality of data segments sufficient to express the digital input signal and selectively provide power to the processing elements of each signal path for selectively processing each data segment in the subset of data segments.

2 . The system of claim 1 , wherein the subset of data segments comprises data segments required for a combination of the subset of data segments to express the digital input signal, and wherein the configuration controller is operable to feed the required data segments to corresponding processing elements.

3 . The system of claim 1 , further comprising an envelope detector operable to determine which of the plurality of data segments are sufficient to form a combination to express the digital input signal.

4 . The system of claim 1 , wherein each of the plurality of data segments has a weight corresponding to a level of amplitude of the digital input signal and the configuration control is operable to provide power to the processing elements corresponding to the data segments of a minimum weight up to and including the data segment having the weight corresponding to a current amplitude of the input signal.

5 . The system of claim 1 , further comprising:
a dynamic element matching module arranged to receive an output of the data splitter and a control signal from configuration controller, the dynamic element matching module operable to receive one of the data segments and perform data shuffling on the data segment when enabled by the configuration controller.

6 . The system of claim 1 , further comprising:
a digital-to-analog converter controlled by the configuration controller, the digital-to-analog converter operable to receive one of the data segments and produce an analog signal at a gain corresponding to a determined weight of the received one of the data segments.

7 . The system of claim 1 , wherein the data splitter further comprises a plurality of digital modulators controlled by the configuration controller, the plurality of digital modulators operable to generate data segments having weights corresponding to a level of amplitude of the digital input signal, the each data segment having a weight corresponding to a level of amplitude from a minimum amplitude up to and including a weight corresponding to a current amplitude of the input signal.

8 . A digital-to-analog conversion system comprising:
a data splitter operable to split a digital input signal into a plurality of data segments, wherein the digital input signal is expressed as a combination of one or more of the plurality of data segments; a plurality of signal paths, each signal path having a plurality of processing elements operable to receive and process a corresponding one of the plurality of data segments; and a configuration controller operable to selectively supply power to processing elements used for processing the plurality of data segments, wherein the configuration controller disables processing elements not required for a subset of data segments to express the digital input signal.

9 . The system of claim 8 , wherein the configuration controller is operable to bypass processing elements corresponding to the plurality of data segments not required for the subset to express the digital input signal.

10 . The system of claim 8 , further comprising an envelope detector operable to determine which of the plurality of data segments are not required for the subset to express the digital input signal.

11 . The system of claim 8 , wherein each of the plurality of signal paths has an associated weight corresponding to a level of amplitude of the digital input signal and wherein the configuration controller is operable to selectively supply power to the processing elements used for processing the plurality of data segments corresponding to a minimum weight up to and including the data segment having the weight corresponding to a current amplitude of the input signal.

12 . The system of claim 8 , further comprising:
a dynamic element matching module connected to the data splitter and controlled by the configuration controller, the dynamic element matching module operable to receive a corresponding one of the data segments and perform data shuffling on the data segment when enabled by the configuration control.

13 . The system of claim 8 , wherein each signal path has an associated weight corresponding to a level of amplitude of the digital input signal, the system further comprising a digital-to-analog converter controlled by the configuration controller and operable to receive a corresponding one of the data segments and produce an analog signal at a gain corresponding to a weight of the data segment.

14 . The system of claim 12 , wherein each data segment has a weight corresponding to a level of amplitude of the digital input signal, the system further comprising a digital-to-analog converter controlled by the configuration controller and operable to receive a corresponding one of the shuffled data segments from the dynamic element matching module and produce an analog signal at a gain corresponding to a weight of the data segment.

15 . A method of converting a digital input signal to an analog signal, the method comprising:
splitting the digital input signal into a plurality of data segments, wherein each data segment comprises a portion of the digital input signal such that the digital input signal is expressed by a weighted sum of the data segments, wherein at least one data segment having a minimum weight is required for the weighted sum to express the digital input signal; and controlling a configuration of a signal processor to selectively enable and disable processing elements used for processing the data segments, wherein data segments that are required for the weighted sum to express the digital input signal are enabled, and data segments that are not required for the weighted sum to express the digital input signal are disabled.

16 . The method of claim 15 , further comprising:
controlling the configuration of the signal processor to feed the data segments required for the weighted sum to express the digital input signal to processing elements used for processing those data segments, and to bypass those processing elements corresponding to data segments that are not required for the weighted sum to express the digital input signal.

17 . The method of claim 15 , further comprising:
determining which of the plurality of data segments are required for the weighted sum to express the digital input signal.

18 . The method of claim 15 , further comprising:
assigning a weight to each data segment such that each weight corresponds to a range of amplitude values of the digital input signal; and controlling the configuration of the signal processor to selectively provide power to the processing elements corresponding to the data segments of a minimum weight up to and including the data segment having the weight corresponding to a current amplitude of the input signal.

19 . The met

Assignees

• Synaptics Inc

Inventors

• Crespi Lorenzo
• De Berti Claudio

Classifications

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• G06F3/165

  Management of the audio stream, e.g. setting of volume, audio stream path · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M3/502

  Details of the final digital/analogue conversion following the digital delta-sigma modulation · CPC title

• H03M3/338 Primary

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title