Envelope-dependent noise-shaped segmentation in oversampling digital-to-analog converters

Patent metadata

Field	Value
Publication number	US-9735799-B1
Application number	US-201615223220-A
Country	US
Kind code	B1
Filing date	Jul 29, 2016
Priority date	Jul 29, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Improved mechanisms for applying noise-shaped segmentation techniques in a multi-bit DAC are disclosed. Noise-shaped segmentation refers to constructing two or more noise-shaped signals whose sum equals the original digital input signal by splitting each word of the input signal into two or more sub-words and converting each sub-word by a respective sub-word DAC group. Disclosed mechanisms include determining a range of amplitudes of a portion of the input signal over a certain time period, and, when converting digital words of that portion to analog values, limiting the number of sub-word DAC groups which are used for the conversion only to a number that is necessary for generating an analog output corresponding to the portion being evaluated, which number is determined based on the tracked amplitudes and could be smaller than the total number of sub-word DAC groups. Placing unused sub-word DAC groups into a power saving mode reduces power consumption.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) for implementing one or more noise-shaped segmentation techniques, the DAC comprising:
a plurality of sub-word DAC groups, where each sub-word DAC group is configured to convert a different sub-word of a plurality of sub-words split from an input word, where at least two of the plurality of sub-words have one or more bits overlapping, and
a controller configured to:
determine a range of amplitudes of at least a portion of an input signal comprising the input word;
select one or more sub-word DAC groups of the plurality of sub-word DAC groups for conversion of the portion of the input signal, the selected one or more sub-word DAC groups corresponding to the determined range of amplitudes of the portion of the input signal; and
limit the conversion of the portion of the input signal to using the selected one or more sub-word DAC groups.

2. The DAC according to claim 1 , wherein limiting the conversion of the portion of the input signal to using the selected one or more sub-word DAC groups comprises setting one or more sub-word DAC groups of the plurality of sub-word DAC groups which were not selected for the conversion to be in a low-power mode during the conversion.

3. The DAC according to claim 2 , wherein each of the plurality of sub-word DAC groups comprises a plurality of three-level DAC cells, and wherein setting the one or more sub-word DAC groups which were not selected for the conversion to be in the low-power mode comprises setting the DAC cells of the one or more sub-word DAC groups which were not selected for the conversion to conduct zero current from supply to ground.

4. The DAC according to claim 2 , wherein each of the plurality of sub-word DAC groups comprises a plurality of three-level DAC cells, and wherein setting the one or more sub-word DAC groups which were not selected for the conversion to be in the low-power mode comprises ensuring that b, b_bar, and z switches of each of the plurality of three-level DAC cells are open.

5. The DAC according to claim 2 , wherein when the conversion of the portion of the input signal is limited to using the selected one or more sub-word DAC groups, digital components associated with each of one or more sub-word DAC groups not selected for the conversion are operating as if the one or more sub-word DAC groups not selected for the conversion were selected.

6. The DAC according to claim 1 , wherein limiting the conversion of the portion of the input signal to using the selected one or more sub-word DAC groups comprises routing the input signal from one of the sub-word DAC groups not selected for the conversion to one of the sub-word DAC groups selected for the conversion.

7. The DAC according to claim 1 , wherein the controller is configured to determine the range of amplitudes by receiving data indicative of the range of amplitudes as measured by a peak detector.

8. The DAC according to claim 1 , wherein the controller is further configured to:
determine whether the range of amplitudes of the portion of the input signal is smaller than a threshold value,
wherein the one or more sub-word DAC groups selected for the conversion are selected based on the threshold value when it is determined that the range of amplitudes of the portion of the input signal is smaller than the threshold value.

9. The DAC according to claim 8 , wherein:
the threshold value is one of a plurality of threshold values,
determining whether the range of amplitudes of the portion of the input signal is smaller than the threshold value comprises determining whether the range of amplitudes of the portion of the input signal is smaller than the threshold value for two or more of the plurality of threshold values, and
the controller is configured to select the one or more sub-word DAC groups for conversion based on the smallest threshold value of the plurality of threshold values for which it was determined that the range of amplitudes of the portion of the input signal is smaller than the threshold value.

10. The DAC according to claim 8 , wherein the controller is further configured to:
following the limitation of the conversion of the portion of the input signal to using the selected one or more sub-word DAC groups, determine a further range of amplitudes of a further portion of the input signal and removing the limitation when the further range of amplitudes is determined to be equal to or greater than the threshold value.

11. The DAC according to claim 8 , wherein the threshold value is equal to a fraction of the full scale of the DAC.

12. The DAC according to claim 1 , wherein the DAC is a multi-bit sigma-delta DAC.

13. The DAC according to claim 1 , wherein the DAC is configured to implement one or more noise-shaped segmentation techniques for splitting the input word into the plurality of sub-words.

14. The DAC according to claim 1 , wherein at least one of the at least two of the plurality of sub-words that have one or more bits overlapping comprises at least two bits.

15. A method for controlling application of one or more noise-shaped segmentation techniques in a digital-to-analog converter (DAC), the method comprising:
splitting an input word into a plurality of sub-words, where at least two of the plurality of sub-words have one or more bits overlapping;
determining a range of amplitudes of at least a portion of an input signal comprising the input word;
selecting one or more sub-word DAC groups of a plurality of sub-word DAC groups of the DAC for conversion of the portion of the input signal, the selected one or more sub-word DAC groups corresponding to the determined range of amplitudes of the portion of the input signal; and
limiting the conversion of the portion of the input signal to using the selected one or more sub-word DAC groups.

16. The method according to claim 15 , wherein limiting the conversion of the portion of the input signal to using the selected one or more sub-word DAC groups comprises setting one or more sub-word DAC groups of the plurality of sub-word DAC groups which were not selected for the conversion to be in a low-power mode during the conversion.

17. The method according to claim 16 , wherein each of the plurality of sub-word DAC groups comprises a plurality of three-level DAC cells, and wherein setting the one or more sub-word DAC groups which were not selected for the conversion to be in the low-power mode comprises turning the DAC cells of the one or more sub-word DAC groups which were not selected for the conversion off.

18. The method according to claim 16 , wherein each of the plurality of sub-word DAC groups comprises a plurality of three-level DAC cells, and wherein setting the one or more sub-word DAC groups which were not selected for the conversion to be in the low-power mode comprises ensuring that b, b_bar, and z switches of each of the plurality of three-level DAC cells are open.

19. The method according to claim 15 , wherein limiting the conversion of the portion of the input signal to using the selected one or more sub-word DAC groups comprises routing the input signal from one of the sub-word DAC groups not selected for the conversion to one of the sub-word DAC groups selected for the conversion.

20. The method according to claim 15 , further comprising determining whether the range of amplitudes of the portion of the input signal is smaller than a threshold value, wherein the one or more sub-word DAC groups selected for the conversion are selected based on the threshold valu

Assignees

• Analog Devices Inc

Inventors

• Nguyen Khiem Quang

Classifications

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/06 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title