DC-coupled high-voltage level shifter

Patent metadata

Field	Value
Publication number	US-11658654-B2
Application number	US-202117225647-A
Country	US
Kind code	B2
Filing date	Apr 8, 2021
Priority date	Jun 19, 2017
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

First claim

The invention claimed is:

1. A level shifter, comprising:
low voltage transistor devices configured to operate between a first voltage and a second voltage;
a first terminal configured to carry the first voltage;
a second terminal configured to carry the second voltage substantially corresponding to a sum of the first voltage and a low voltage;
input nodes configured to receive input timing control signals;
a parallel resistive-capacitive network coupled between the input nodes and the low voltage transistor devices; and
an output node configured to provide an output timing control signal, the output timing control signal being based on signal information of the input timing control signals through the parallel resistive-capacitive network.

2. The level shifter of claim 1 , wherein the first voltage is equal to or higher than 10 volts, and the low voltage is equal to or lower than 5 volts.

3. The level shifter of claim 1 , wherein the first voltage is equal to or higher than 25 volts, and the low voltage is equal to or lower than 2.5 volts.

4. The level shifter of claim 1 , wherein the low voltage transistor devices are configured to withstand a voltage that is equal to or lower than the low voltage.

5. The level shifter of claim 1 , wherein the output timing control signal is at a voltage that is higher than the first voltage.

6. The level shifter of claim 1 , wherein the low voltage is substantially lower than the first voltage.

7. The level shifter of claim 1 , wherein the input nodes comprise two input nodes, each configured to receive edge information and DC level information of the input timing control signals.

8. The level shifter of claim 1 , wherein:
the parallel resistive-capacitive network comprises two parallel resistive-capacitive networks, each coupled to:
i) a respective one of the two input nodes for receiving a respective one of two complementary input timing control signals, and
ii) a respective one of two common nodes coupled to the low voltage transistor devices.

9. The level shifter of claim 1 , wherein:
the parallel resistive-capacitive network comprises a resistive conduction path comprising one or more series connected resistors and a capacitive conduction path comprising one or more series connected capacitors.

10. The level shifter of claim 1 , wherein the level shifter further comprises:
a capacitor that is coupled between a node that is common to the parallel resistive-capacitive network and to the low voltage transistor devices, and the second terminal; and
a resistor that is coupled between said node and the second terminal.

11. The level shifter of claim 10 , wherein the level shifter further comprises:
a capacitor that is coupled between the node that is common to the parallel resistive-capacitive network and to the low voltage transistor devices, and the first terminal; and
a resistor that is coupled between said node and the first terminal.

12. The level shifter of claim 1 , wherein the low voltage transistor devices comprises a plurality of low voltage transistor devices that are configured to operate as a flying comparator, the flying comparator comprising: differential input nodes coupled to the parallel resistive-capacitive network; and complementary output nodes.

13. The level shifter of claim 12 , wherein the low voltage transistor devices further comprises a plurality of low voltage transistor devices that are configured as clamp circuits to limit an instantaneous voltage across nodes of the plurality of low voltage transistor devices of the flying comparator during a switching event of the first voltage.

14. The level shifter of claim 1 , further comprising a charge pump circuit configured to amplify the input timing control signals.

15. A level shifter, comprising:
low voltage transistor devices configured to operate in a flying voltage domain defined by a first voltage and a low voltage;
input nodes configured to receive input timing control signals;
a parallel resistive-capacitive network configured to couple the input nodes and the low voltage transistor devices; and
an output node configured to provide an output timing control signal, the output timing control signal being based on signal information of the input timing control signals through the parallel resistive-capacitive network.

16. The level shifter of claim 15 , wherein the low voltage transistor devices are configured to withstand a voltage that is equal to or lower than the low voltage, the low voltage being lower than the first voltage.

17. A high voltage switching device comprising the level shifter of claim 16 .

18. The high voltage switching device of claim 17 , further comprising a high voltage transistor device configured to withstand the first voltage, wherein operation according to an ON mode and an OFF mode of the high voltage transistor device is controlled by the level shifter.

19. The high voltage switching device of claim 18 , wherein during the ON mode of operation, a voltage at a source terminal of the high voltage transistor device is substantially equal to the first voltage, and during the OFF mode of operation, a voltage at the source terminal of the high voltage transistor device is substantially equal to a reference voltage.

20. A DC/DC converter for conversion of a high DC voltage to a low DC voltage comprising the high voltage switching device of claim 19 .

21. A method for controlling a high voltage device, the method comprising:
providing a plurality of low voltage devices configured to withstand a voltage equal to or lower than a low voltage;
operating the plurality of low voltage devices in a flying voltage domain defined by a first voltage and the low voltage, the first voltage higher than the low voltage;
coupling input timing control signals to the plurality of low voltage devices via a parallel resistive-capacitive network;
based on the coupling, transmitting signal information of the input timing control signals to the low voltage devices;
based on the operating and the transmitting, generating, via the plurality of low voltage devices, an output timing control signal at a voltage higher than the first voltage; and
based on the generating, controlling the high voltage device.

Assignees

• Psemi Corp

Inventors

• Wu Gary Chunshien

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D86/03

  wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS] · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title