Dead time control circuit for a level shifter

Patent metadata

Field	Value
Publication number	US-10044347-B2
Application number	US-201715842753-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Mar 18, 2015
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

First claim

The invention claimed is:

1. A circuital arrangement configured to control a high side (HS) device and a low side (LS) device arranged in a stacked configuration, the HS device and the LS device capable of withstanding a voltage higher than or equal to a first voltage, the circuital arrangement comprising:
a HS control circuit operating between a first switching voltage and a second switching voltage based on the first switching voltage, the first switching voltage being an output voltage at a common output node of the stacked HS device and LS device, the HS control circuit configured to provide a HS output control signal at a voltage higher than the first voltage to the HS device;
a LS control circuit configured to provide a LS output control signal to the LS device; and
a dead time control circuit configured, to generate timing information for the HS output control signal and the LS output control signal,
wherein all transistor devices of the HS control circuit, the LS control circuit and the dead time controller circuit, are each configured to withstand a second voltage substantially smaller than the first voltage,
wherein the timing information for the HS output control signal is coupled to the transistor devices of the HS control circuit by way of a DC blocking edge detection circuit comprising:
i) a first capacitive coupling configured to receive a first HS input timing control signal containing the timing information for the HS output control signal, and
ii) a second capacitive coupling configured to receive a second HS input timing control signal that is an inverted version of the first input timing control signal, wherein:
each of the first and second capacitive couplings comprises two series connected capacitors and a common node between the series connected capacitors, the common node configured to receive a respective one of the first and the second HS input timing control signals,
for each of the first and second capacitive couplings, a first capacitor of the two series connected capacitors is coupled via a resistor connected to a terminal of the first capacitor away from the common node to the first switching voltage, so to generate a positive pulse (CUvss, CDvss) in correspondence of a rising edge of a respective input timing control signal (CUb, CDb) and no pulse in correspondence of a falling edge of said input timing control signal,
for each of the first and second capacitive couplings, a second capacitor of the two series connected capacitors is coupled via a resistor connected to a terminal of the second capacitor away from the common node to the second switching voltage, so to generate a negative pulse (CUvdd, CDvdd) in correspondence of a falling edge of the respective input timing control signal (CUb, CDb) and no pulse in correspondence of a rising edge of said input timing control signal, and
a first edge of the HS output control signal corresponds to concurrent detection of the positive pulse in correspondence of the rising edge of the first input timing control signal and the negative pulse in correspondence of the falling edge of the second input timing control signal, and a second edge of the HS output control signal corresponds to concurrent detection of the positive pulse in correspondence of the rising edge of the second input timing control signal and the negative pulse in correspondence of the falling edge of the first input timing control signal.

2. The circuital arrangement of claim 1 , wherein:
the HS output control signal comprises a first pulse in correspondence of an ON state of the HS device, the first pulse defined by the first edge and the second edge of the HS output control signal,
the LS output control signal comprises a second pulse in correspondence of an ON state of the LS device,
the first pulse and the second pulse are non-overlapping, and
a pulse width of the first pulse is substantially equal to a pulse width of an input pulse to the dead time control circuit.

3. The circuital arrangement of claim 1 , wherein the dead time controller circuits further comprises:
a HS processing path configured to generate the timing information of the HS output control signal; and
a LS processing path configured to generate the timing information of the LS output control signal.

4. The circuital arrangement of claim 3 , wherein the timing information is based on one or both of a) an adjusted position of a rising edge of an input signal, and b) an adjusted position of a falling edge of the input signal.

5. The circuital arrangement of claim 4 , wherein the HS processing path and the LS processing path each comprise two processing circuits.

6. The circuital arrangement of claim 5 , wherein each of the processing circuits performs an adjustment of one of a) the rising edge of the input signal, and b) the falling edge of the input signal.

7. The circuital arrangement of the claim 6 , wherein each of the processing circuits comprises a transistor, a current source, a capacitor and a comparator.

8. The circuital arrangement of claim 6 , wherein each of the processing circuits comprises a transistor, a current source, a capacitor and an inverter.

9. The circuital arrangement of claim 8 , wherein the adjustment is based on a time delay, with respect to one of a) the rising edge of the input signal, and b) the falling edge of the input signal, provided by the current source, the capacitor and a trip point voltage of the inverter.

10. The circuital arrangement of claim 9 , wherein the current source comprises control circuitry configured to adjust a magnitude of an output current of the current source based on a variation of the trip point voltage of the inverter.

11. The circuital arrangement of claim 10 , wherein the variation of the trip point voltage is based on one or more of a) a fabrication process of the inverter, b) a voltage supply to the inverter and c) an operating temperature of the inverter.

12. The circuital arrangement of claim 10 , wherein the magnitude of the output current is controlled by a reference resistor.

13. The circuital arrangement of claim 10 , wherein the control circuitry comprises:
an operational amplifier;
a current mirror;
a reference inverter with same characteristics as the inverter of the basic processing circuit, the reference inverter coupled to a first input of the operational amplifier;
a transistor, wherein a gate of the transistor is connected to an output of the operational amplifier, a source of the transistor connected to a second input of the operational amplifier, and a drain of the transistor connected to a reference current leg of the current mirror; and
the reference resistor connected between the source of the transistor and a reference ground.

14. The circuital arrangement of claim 13 , wherein the reference inverter comprises two series connected transistors, wherein gates and drains of the series connected transistors are connected to the first input of the operational amplifier.

15. The circuital arrangement of claim 1 , wherein the first voltage is equal to or higher than 10 volts, and the second voltage is equal to or lower than 5 volts.

16. The circuital arrangement of claim 1 , wherein the first voltage is equal to or higher than 25 volts, and the second voltage is equal to or lower than 2.5 volts.

17. The circuital arrangement of claim 1 , wherein the transistor devices comprise one of: a) a silicon on sapphire (SOS) transistor structure, b) a silicon on insulator (SOI) transistor structure, and c) a bulk silicon (Si) transistor structure.

18. The circui

Assignees

• Psemi Corp

Inventors

• Abesingha Buddhika
• Green Merlin

Classifications

• H03K2005/00019

  Variable delay · CPC title

• H02M1/38

  Means for preventing simultaneous conduction of switches · CPC title

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H02M7/538

  in a push-pull configuration (H02M7/5375 takes precedence {; with oscillating arrangements H02M7/53832, H02M7/53846}) · CPC title

• H03K5/1534

  Transition or edge detectors · CPC title