Three-dimensional memory device with source structure and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11653495-B2
Application number	US-202117185963-A
Country	US
Kind code	B2
Filing date	Feb 26, 2021
Priority date	Aug 13, 2019
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. A cut structure is first formed in a stack structure. The stack structure includes interleaved initial sacrificial layers and initial insulating layers. A patterned cap material layer is formed over the stack structure. The patterned cap material layer includes an opening over the cut structure. Portions of the stack structure and the patterned cap material layer adjacent to the opening are removed to form a slit structure and an initial support structure. The initial support structure divides the slit structure into slit openings. Conductor portions are formed through the plurality of slit openings to form a support structure. A source contact is formed in each slit opening. A connection layer is formed over the source contact in each slit opening and over the support structure.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a cut structure in a stack structure, the stack structure comprising interleaved a plurality of initial sacrificial layers and a plurality of initial insulating layers;
forming a patterned cap material layer over the stack structure, the patterned cap material layer comprising an opening over the cut structure;
removing portions of the stack structure and the patterned cap material layer adjacent to the opening to form a slit structure and an initial support structure, the initial support structure dividing the slit structure into a plurality of slit openings;
forming a plurality of conductor portions through the plurality of slit openings to form a support structure;
forming a source contact in each of the plurality of slit openings; and
forming a connection layer over the source contact in each of the plurality of slit openings and over the support structure.

2. The method of claim 1 , wherein forming the cut structure comprises:
patterning the stack structure to form a cut opening in a source region; and
depositing a dielectric material to fill up the cut opening.

3. The method of claim 1 , wherein forming the patterned cap material layer comprises:
depositing a cap material layer to cover the source region; and
removing a portion of the cap material layer to form the opening over the cut structure.

4. The method of claim 3 , wherein removing portions of the stack structure and the patterned cap material layer adjacent to the opening comprises removing portions of the stack structure and the patterned cap material layer in the source region and adjacent to the cut structure and the opening, such that:
the opening is in contact with adjacent slit openings;
each of the plurality of slit openings exposes the substrate;
the cut structure and interleaved a plurality of sacrificial portions and a plurality of insulating portions form the initial support structure; and
a cap layer is formed surrounding the slit structure along a lateral direction in which the slit structure extends.

5. The method of claim 1 , wherein forming the plurality of conductor portions comprises:
removing, through the plurality of slit openings, the plurality of sacrificial portions in the initial support structure to form a plurality recess portions; and
depositing a conductor material to fill up the plurality of recess portions to form the plurality of conductor portions, the initial support structure forming a support structure.

6. The method of claim 5 , further comprising forming a plurality of conductor layers in a plurality of block portions of the stack structure in the same operations that form the plurality of conductor portions, such that the plurality of block portions is in contact with the initial support structure, wherein the plurality of conductor layers are formed by:
removing, through the plurality of slit openings, a plurality of sacrificial layers in the plurality of block portions to form a plurality of lateral recesses; and
depositing the conductive material to fill up the plurality of lateral recesses to form the plurality of conductor layers.

7. The method of claim 5 , wherein forming the source contact comprises depositing a conductive material into the respective slit opening, such that a top surface of the source contact is lower than a top surface of the support structure along the vertical direction.

8. The method of claim 7 , wherein forming the connection layer comprises depositing a conductive material to fill up a space formed by a portion of the slit structure not filled with the source structure and the cap layer.

9. The method of claim 6 , further comprising:
depositing an adhesion layer between in each of the plurality of slit openings; and forming an insulating structure in the slit opening before forming the source contact.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xu Wenxiang
• Xu Wei
• Huang Pan
• Yan Ping
• Huo Zongliang
• Zhou Wenbin
• Xia Ji

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title