Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9520403-B2
Application number	US-201514803776-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Jun 24, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a plurality of stacks isolated through slits and including a plurality of first material layers and a plurality of second material layers alternately stacked;
partially removing the first material layers to form a plurality of grooves placed at both sides of the plurality of stacks, wherein parts of the first material layers remain at the centers of the plurality of stacks as spacers; and
forming conductive layers in the plurality of grooves.

2. The method of claim 1 , further comprising forming channel layers passing through the plurality of stacks, arranged in a direction, and offset by their centers.

3. The method of claim 2 , wherein each of the channel layers includes a source-side channel layer, a drain-side channel layer, and a pipe channel layer connecting the source-side channel layers and the drain-side channel layers.

4. The method of claim 3 , wherein each of the spacers is placed between the source-side channel layer and the drain-side channel layer connected through one pipe channel layer, and each of the slits are placed between the channel layers adjacent to each other.

5. The method of claim 3 , wherein each of the spacers is placed between the channel layers adjacent to each other, and each of the slits is placed between the source-side channel layer and the drain-side channel layer connected through one pipe channel layer.

6. The method of claim 1 , wherein each of the spacers includes at least one of oxide, nitride, or titanium.

7. The method of claim 1 , wherein the conductive layers and the spacers extend in a same direction.

8. The method of claim 1 , wherein each of the spacers is sandwiched between the second material layers disposed at different levels.

9. The method of claim 1 , wherein the conductive layers and the spacers extend in the same direction.

10. The method of claim 1 , wherein the spacers and the conductive layers are located on the same level.

11. The method of claim 10 , wherein the conductive layers located on the same level are insulated from each other by the spacers.

12. A method of manufacturing a semiconductor memory device, the method comprising:
forming first material layers and second material layers alternately stacked;
forming slits passing through the first material layers and the second material layers;
forming channel layers passing through the first material layers and the second material layers;
partially removing the first material layers through the slits to form grooves, wherein first material patterns remain between the channel layers; and
forming conductive layers in the grooves, wherein the first material patterns are interposed between the conductive layers at the same level.

Assignees

• Sk Hynix Inc

Inventors

• Ahn Jung Ryul
• Lee Yun Kyoung

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic