Hybrid logical to physical caching scheme of L2P cache and L2P changelog

Patent metadata

Field	Value
Publication number	US-11650931-B2
Application number	US-202117234062-A
Country	US
Kind code	B2
Filing date	Apr 19, 2021
Priority date	Dec 31, 2018
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

First claim

What is claimed is:

1. A system comprising:
a processing device configured to execute instructions stored on one or more components in the system, which instructions, when executed by the processing device cause the processing device to perform operations to:
control access to a logical to physical (L2P) cache in a storage device and to a L2P changelog in the storage device with the L2P cache being different from the L2P changelog, the L2P changelog arranged having entries, each of the entries containing a pair defined by a logical block address and a physical address to which the logical block address is mapped in a memory system; and
access a page pointer table in the L2P cache, in performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address received from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog using a coldness index of the page pointer table to load the page pointer table, wherein, with the L2P cache configured with multiple page pointer tables, the processing device is operable to adjust a coldness index of each page pointer table of the multiple page pointer tables of the L2P cache when a different page pointer table is accessed.

2. The system of claim 1 , wherein the operations include defining a cold status of the coldness index, of the page pointer table, using an association of a time interval with write operations.

3. The system of claim 1 , wherein the adjustment of the coldness indexes is in response to the different page pointer table, of the L2P cache, being accessed for a read operation or a write operation, where coldness index, of the different page pointer table, is not adjusted.

4. The system of claim 1 , wherein the adjustment of the coldness indexes is in response to the different page pointer table being a page pointer table in the L2P changelog being accessed for a read operation or a write operation.

5. The system of claim 1 , wherein, with the L2P cache configured with a first set of page pointer tables and the L2P changelog configured with a second set of page pointer tables, the processing device is operable to:
transfer one or more page pointer tables of the first set to a non-volatile memory based on a coldness index of each of the one or more page pointer tables of the first set; and
transfer one or more page pointer tables of the second set to the L2P cache from the L2P changelog based on a coldness index of each of the one or more page pointer tables of the second set.

6. A system comprising:
a processing device configured to execute instructions stored on one or more components in the system, which instructions, when executed by the processing device cause the processing device to perform operations to:
control access to a logical to physical (L2P) cache in a storage device and to a L2P changelog in the storage device with the L2P cache being different from the L2P changelog, the L2P changelog arranged having entries, each of the entries containing a pair defined by a logical block address and a physical address to which the logical block address is mapped in a memory system; and
access a page pointer table in the L2P cache, in performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address received from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog using a coldness index of the page pointer table to load the page pointer table, wherein the processing device is operable to adjust a hit rate on the L2P cache with respect write and read operations by configuring the L2P cache with most frequently accessed page pointer tables based on latest accesses by the host.

7. The system of claim 6 , wherein the processing device is operable to use both the L2P cache and the L2P changelog in write and read operations in the memory system.

8. The system of claim 6 , wherein the page pointer table is loaded into the L2P cache from the L2P changelog in response to a determination that the coldness index identifies the page pointer table as having a hot status.

9. The system of claim 6 , wherein the storage device is a volatile memory device.

10. A system comprising:
a memory device;
a storage device;
a processing device configured to execute instructions stored on one or more components in the system, which instructions, when executed by the processing device cause the processing device to perform operations to:
control access to the storage device arranged to include:
a logical to physical (L2P) cache with the L2P cache divided in slots of page pointer tables, each page pointer table arranged as an array of physical addresses; and
a L2P changelog with the L2P changelog being different from the L2P cache and with the L2P changelog having entries arranged as page pointer table lists, each page pointer table list containing one or more pairs of logical block addresses with physical addresses, each of the pairs includes a logical block address mapped to a physical address in the memory device; and

manage L2P mapping by transferring a selected page point table out of the L2P cache based on a cold status of the selected page point table and transferring an identified page point table in the L2P changelog to the L2P cache based on a hot status of a page pointer table list associated with the identified page point table.

11. The system of claim 10 , wherein the hot status that initiates the transfer of the identified page point table is an arrival of a pair element to the page pointer table list after the page pointer table list has been filled to a maximum number of pair elements.

12. The system of claim 11 , wherein the processing device is operable to:
transfer the selected page point table out of the L2P cache by loading the selected page point table to a non-volatile memory device; and
remove the page pointer table list, associated with the identified page point table, from the L2P changelog.

13. The system of claim 10 , wherein the processing device is operable to manage L2P mapping by identifying one or more page pointer tables in the L2P cache to be in a coldest status with respect to a total number of page pointer tables in the L2P cache and loading the identified one or more page pointers to a non-volatile memory device from the storage device.

14. The system of claim 10 , wherein the processing device is operable, in a write operation, to update a target page pointer table in the L2P cache with new address information of data of the write operation.

15. A method comprising:
controlling access to a logical to physical (L2P) cache in a storage device and access to a L2P changelog in the storage device with the L2P cache being different from the L2P changelog, the L2P changelog having entries, each of the entries containing a pair defined by a logical block address and a physical address to which the logical block address is mapped in a memory system;
accessing a page pointer table in the UP cache, in performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address received from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog using a coldness index of the page pointer table to load the page pointer table; and
arranging the L2P changelog as a clustering of page pointer tables, with each page pointer table having one or more pairs of logical block addresses and physical addresses.

16. A

Assignees

• Micron Technology Inc

Inventors

• Manganelli Carminantonio
• Weinberg Yoav
• Sassara Alberto
• Papa Paolo
• Esposito Luigi
• D'Eliseo Giuseppe
• Della Monica Angelo
• Iaculo Massimo

Classifications

• G06F2212/466

  Metadata, control data · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title