Semiconductor device for managing cold addresses of nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-10877698-B2
Application number	US-201916434001-A
Country	US
Kind code	B2
Filing date	Jun 6, 2019
Priority date	Jul 5, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A semiconductor device may include a media controller configured to output a write requested address when a write request to a nonvolatile memory device is provided from a host; and a cold address manager. The cold address manager may include a stack storing meta data for the write requested address, region information storage configured to manage addresses of the nonvolatile memory device with regions such that length of a region of the regions may vary after a predetermined period, a cold address detector configured to update the stack and the region information storage after the predetermined period and to detect whether an address of the nonvolatile memory device is a cold address, the cold address having write requests performed at less than a predetermined level.

First claim

What is claimed is:

1. A semiconductor device comprising:
a media controller configured to output a write requested address in response to a write request to a nonvolatile memory device provided from a host; and
a cold address manager comprising a stack storing meta data for the write requested address, a region information storage configured to manage addresses of the nonvolatile memory device with regions wherein a length of a region of the regions is altered after a predetermined period, a cold address detector configured to update the stack and the region information storage after the predetermined period and to detect whether an address of the nonvolatile memory device is a cold address, the cold address having write requests performed at less than a predetermined level,
wherein the region information storage is initialized to store a plurality of region information such that all addresses of the nonvolatile memory device have a corresponding region in the plurality of region information, and
wherein each of the plurality of the region information includes an address field to store an address of a nonvolatile memory device related to a corresponding region, a state field storing a value representing a coldness property of the corresponding region, and a pointer field storing an address of a region related to the corresponding region.

2. The semiconductor device of claim 1 , wherein the cold address manager further comprises a cold address storage to store the cold address.

3. The semiconductor device of claim 1 , wherein the nonvolatile memory device performs a write operation according to a page basis, wherein each of the regions is initially related to a plurality of pages, and wherein the cold address detector periodically updates the region information storage by increasing or decreasing a number of pages related to a region referring to region information thereof and updated the meta data on the stack accordingly.

4. The semiconductor device of claim 1 , wherein the stack is initially vacant.

5. The semiconductor device of claim 1 , wherein the region information storage includes a first data structure and a second data structure, wherein the first data structure includes a data structure whose memory space is pre-allocated, and the second data structure includes a data structure whose length varies according to generation or deletion of a region related to a region stored in the first data structure.

6. The semiconductor device of claim 5 , wherein the first data structure stores a plurality of region information each is related to a region and the first data structure is initialized such that the plurality of region information are related to all addresses of the nonvolatile memory device.

7. The semiconductor device of claim 1 , wherein the cold address detector periodically updates the state field of each of the plurality of region information according to the meta data stored on the stack.

8. The semiconductor device of claim 7 , wherein the cold address detector merges adjacent region information or splits a region information stored in the region information storage according to the state field.

9. The semiconductor device of claim 8 , wherein the cold address detector merges the adjacent region information in response to the state field at each of the adjacent region information represents maximum coldness.

10. The semiconductor device of claim 9 , wherein the cold address detector splits region information in response to the state field of a region information represents minimum coldness.

11. The semiconductor device of claim 7 , wherein the cold address detector periodically detects region information whose state field represents maximum coldness and stores an address of the nonvolatile memory device related to the region information as a cold address.

12. The semiconductor device of claim 1 , further comprising:
a wear level controller configured to control a wear leveling operation of the nonvolatile memory device using the cold address.

13. The semiconductor device of claim 12 , further comprising a mapping table storing a mapping relation between a logical address and a physical address of the nonvolatile memory device, wherein the wear level controller controls the wear leveling operation by changing the mapping relation using the cold address.

14. The semiconductor device of claim 12 , further comprising a hot address manager configured to detect a hot address where write requests are concentrated and to store the hot address, and wherein the wear level controller controls the wear leveling operation using a hot address provided by the hot address manager and the cold address provided by the cold address manager.

15. The semiconductor device of claim 1 , further comprising a scrubbing controller configured to perform a scrubbing operation on the cold address of the nonvolatile memory device.

16. The semiconductor device of claim 15 , wherein the scrubbing controller is configured to control the media controller to perform a read operation and a write operation on the cold address of the nonvolatile memory device.

17. The semiconductor device of claim 15 , wherein the scrubbing operation is performed at a predetermined interval and the predetermined interval is less than time during which drift phenomenon at the nonvolatile memory device deteriorates data.

18. A semiconductor device comprising:
a media controller configured to output a write requested address in response to a write request to a nonvolatile memory device provided from a host; and
a cold address manager comprising a stack storing meta data for the write requested address, a region information storage configured to manage addresses of the nonvolatile memory device with regions wherein a length of a region of the regions is altered after a predetermined period, a cold address detector configured to update the stack and the region information storage after the predetermined period and to detect whether an address of the nonvolatile memory device is a cold address, the cold address having write requests performed at less than a predetermined level,
wherein the stack is initially vacant, and
wherein the stack includes a region number field including a region number, a hit count field storing a hit count wherein the hit count is increased according to a write request to a region that corresponds to the region number, a frequency count field storing a frequency count wherein the frequency count is decreased according to a write request to an other region that does not correspond to the region number.

Assignees

• Sk Hynix Inc
• Seoul Nat Univ R&Db Foundation

Inventors

• Jung Hyunmin
• Kim Sunwoong
• Lee Hyokeun
• Shin Woojae
• Lee Hyuk-Jae

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/222

  Non-volatile memory · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title