Data prioritization for boot-up procedures
US-2025383818-A1 · Dec 18, 2025 · US
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Iaculo Massimo patents
Iaculo Massimo is listed as an inventor on 86 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Iaculo Massimo |
| Total patents | 86 |
| First publication | Nov 10, 2015 |
| Latest publication | Dec 18, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Read disturb management for memory
US-2025341968-A1 · Nov 6, 2025 · US
Clustered parity for nand data placement schema
US-2025278187-A1 · Sep 4, 2025 · US
Address error checking using counters
US-2025231871-A1 · Jul 17, 2025 · US
Idle mode temperature control for memory systems
US-12353750-B2 · Jul 8, 2025 · US
Clustered parity for NAND data placement schema
US-12321594-B2 · Jun 3, 2025 · US
Read disturb management for memory
US-12314566-B2 · May 27, 2025 · US
Data relocation operation techniques
US-12293101-B2 · May 6, 2025 · US
NAND data placement schema
US-12277979-B2 · Apr 15, 2025 · US
Device fault condition reporting
US-2025061021-A1 · Feb 20, 2025 · US
Recent patents
Latest publications not already listed above.
Idle mode temperature control for memory systems
US-2024419353-A1 · Dec 19, 2024 · US
Corrupted storage portion recovery in a memory device
US-2024394183-A1 · Nov 28, 2024 · US
Data caching for fast system boot-up
US-2024303087-A1 · Sep 12, 2024 · US
Device fault condition reporting
US-12079077-B2 · Sep 3, 2024 · US
Optimizing a memory sub-system partition configuration using simulation
US-2024281155-A1 · Aug 22, 2024 · US
Data relocation operation techniques
US-2024272820-A1 · Aug 15, 2024 · US
Corrupted storage portion recovery in a memory device
US-12056046-B2 · Aug 6, 2024 · US
Nand logical-to-physical table region tracking
US-2024248639-A1 · Jul 25, 2024 · US
Idle mode temperature control for memory systems
US-12039189-B2 · Jul 16, 2024 · US
Allocation schema for a scalable memory area
US-11972294-B2 · Apr 30, 2024 · US
Real-time trigger to dump an error log
US-11971776-B2 · Apr 30, 2024 · US
Data caching for fast system boot-up
US-11966752-B2 · Apr 23, 2024 · US
NAND data placement schema
US-11955189-B2 · Apr 9, 2024 · US
Nand data placement schema
US-2024112745-A1 · Apr 4, 2024 · US
Read disturb management for memory
US-2024086070-A1 · Mar 14, 2024 · US
NAND logical-to-physical table region tracking
US-11922053-B2 · Mar 5, 2024 · US
Idle mode temperature control for memory systems
US-2024069784-A1 · Feb 29, 2024 · US
Data relocation operation techniques
US-11907556-B2 · Feb 20, 2024 · US
Data defragmentation for a system boot procedure having random indexes indicating a relationship between sequential logical addresses and random logical addresses
US-11847468-B2 · Dec 19, 2023 · US
Clustered parity for nand data placement schema
US-2023367478-A1 · Nov 16, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 84 |
| Lodestar Licensing Group Llc | 2 |
| Iaculo Massimo | 1 |
| Vitale Ornella | 1 |
| D Eliseo Giuseppe | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0679 | 60 |
| G06F12/0246 | 47 |
| G06F2212/7201 | 33 |
| G06F3/0659 | 29 |
| G06F3/0604 | 25 |