Forming a contact for a semiconductor device

Patent metadata

Field	Value
Publication number	US-9917060-B1
Application number	US-201615331331-A
Country	US
Kind code	B1
Filing date	Oct 21, 2016
Priority date	Oct 21, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A method for fabricating a semiconductor device includes forming a gate stack on a semiconductor substrate, forming a source/drain region on an exposed portion of the substrate, and forming a semiconductor material layer on the source/drain region. A first liner layer is deposited on the semiconductor material layer, and a second liner layer is deposited on the first liner layer. A conductive contact material is deposited on the second liner layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device of a PFET and an NFET, the method comprising:
forming a gate stack on a semiconductor substrate;
forming a first source/drain region in the PFET and a second source/drain region in the NFET on an exposed portion of the substrate;
forming a first semiconductor material layer on the first source/drain region in first trenches and a second semiconductor material layer on the second source/drain region in second trenches, wherein the first and second semiconductor material layers are formed by epitaxial growth;
depositing a first liner layer only on the first semiconductor material layer;
depositing a second liner layer on the first liner layer in the PFET and on the, second semiconductor material layer in the NFET: and
depositing a conductive contact material on the second liner layer in the PFET and on the second liner layer in the NFET.

2. The method of claim 1 , wherein the first semiconductor material layer includes crystalline Ge.

3. The method of claim 1 , wherein the first source/drain region includes doped SiGe material.

4. The method of claim 1 , wherein the first liner layer includes a conductive metallic oxide material.

5. The method of claim 1 , wherein the second liner layer includes a metallic material.

6. The method of claim 1 , wherein the second liner layer includes Ti.

7. The method of claim 1 , wherein the semiconductor substrate includes a semiconductor fin.

8. The method of claim 1 , further comprising forming a spacer adjacent to the gate stack prior to forming the first source/drain region.

9. The method of claim 1 , further comprising forming an insulator layer over portions of the substrate and adjacent to the gate stack prior to forming the source/drain region.

10. The method of claim 1 , further comprising performing a planarization process after depositing the conductive contact material.

11. A method for fabricating a semiconductor device of a PFET and an NFET, the method comprising:
forming a gate stack on a semiconductor substrate;
forming a first source/drain region in the PFET and a second source/drain region in the NFET on an exposed portion of the substrate, the first source/drain region including a first dopant;
forming a first semiconductor material layer on the first source/drain region in first trenches and a second semiconductor material layer on the second source/drain region in second trenches, wherein the first and second semiconductor material layers are formed by epitaxial growth;
depositing a first liner layer including a conductive metallic oxide material only on the first semiconductor material layer;
depositing a second liner layer including a metallic material on the first liner layer in the PFET and on the second semiconductor material layer in the NFET; and
depositing a conductive contact material on the second liner layer in the PFET and on the, second liner layer in the NFET.

12. The method of claim 11 , wherein the first semiconductor material layer includes crystalline Ge.

13. The method of claim 11 , wherein the first source/drain region includes doped SiGe material.

14. The method of claim 11 , wherein the second liner layer includes Ti.

15. The method of claim 11 , further comprising forming a spacer adjacent to the gate stack prior to forming the source/drain region.

16. The method of claim 11 , further comprising forming an insulator layer over portions of the substrate and adjacent to the gate stack prior to forming the source/drain region.

17. The method of claim 11 , further comprising performing a planarization process after depositing the conductive contact material.

18. A method for fabricating a semiconductor device, the method comprising:
forming a gate stack on a semiconductor substrate;
forming a first source/drain region and a second source/drain region on exposed portions of the substrate;
forming a semiconductor material layer on the first source/drain region and the second source/drain region;
depositing a first liner layer on the semiconductor material layer over the first source/drain region and the second source/drain region;
removing a portion of the first liner layer from over the second source/drain region;
removing a portion of the semiconductor material layer to expose the second source/drain region;
depositing a second liner layer on the first liner layer and the exposed second source/drain region; and
depositing a conductive contact material on the second liner layer.

19. The method of claim 18 , wherein the first liner layer includes a conductive metallic oxide material, and the second liner layer includes Ti.

Assignees

• IBM

Inventors

• Gluschenkov Oleg
• Liu Zuoguang
• Mochizuki Shogo
• Niimi Hiroaki
• Xie Ruilong

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title