Large area electrostatic dischage for vertical transistor structures

Patent metadata

Field	Value
Publication number	US-9947649-B1
Application number	US-201715488706-A
Country	US
Kind code	B1
Filing date	Apr 17, 2017
Priority date	Apr 17, 2017
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A semiconductor structure including an electrostatic discharge (ESD) diode with an increased junction area and a vertical field effect transistor (FET) formed on a same substrate is provided. The ESD diode is formed by forming a first doped semiconductor segment merging bottom portions of a pair of semiconductor fins and then forming a second doped semiconductor segment having a conductivity type opposite to that of each of the first doped semiconductor segment and the pair of semiconductor fins. A U-shaped p-n junction is present between the second doped semiconductor segment and the first doped semiconductor segment and the second doped semiconductor segment and the pair of semiconductor fins.

First claim

What is claimed is:

1. A semiconductor structure comprising an electrostatic discharge (ESD) diode located in a region of a semiconductor substrate, wherein the ESD diode comprises:
a pair of semiconductor fins extends upwards from a portion of a doped bottom semiconductor layer located over the semiconductor substrate;
a first doped semiconductor segment adjoined the pair of the semiconductor fins;
a second doped semiconductor segment located over the first doped semiconductor segment and laterally contacting an inner sidewall of a channel region of each semiconductor fin in the pair of semiconductor fins; and
a top contact segment located over the second doped semiconductor segment.

2. The semiconductor structure of claim 1 , wherein a p-n junction is present at an interface between the second doped semiconductor segment and each semiconductor fin in the pair of semiconductor fins.

3. The semiconductor structure of claim 1 , further comprising an interlevel dielectric (ILD) fill portion located over the top contact segment.

4. The semiconductor structure of claim 1 , further comprising a sidewall spacer laterally surrounding the top contact segment and the ILD fill portion.

5. The semiconductor structure of claim 1 , further comprising a doped top semiconductor region laterally surrounding a top portion of each semiconductor fin in the pair of semiconductor fins that is located above the channel region of each semiconductor fin.

6. The semiconductor structure of claim 5 , further comprising a protective layer present on an outer sidewall of the channel region of each semiconductor fin in the pair of semiconductor fins.

7. The semiconductor structure of claim 6 , further comprising a sacrificial gate portion laterally contacting each protective layer.

8. The semiconductor structure of claim 7 , further comprising a bottom spacer layer located between the doped bottom semiconductor layer and the sacrificial gate portion.

9. The semiconductor structure of claim 7 , further comprising a top spacer located between each doped top semiconductor region and the sacrificial gate portion.

10. The semiconductor structure of claim 5 , further comprising a metal gate structure laterally contacting an outer sidewall of the channel region of each semiconductor fin of the pair of semiconductor fins.

11. The semiconductor structure of claim 10 , further comprising a vertical field effect transistor (FET) located in another region of the semiconductor substrate, wherein the vertical effect transistor comprises:
another semiconductor fin extends upwards from another portion of the doped bottom semiconductor layer;
another metal gate structure laterally surrounding a channel region of the another semiconductor fin; and
another doped top semiconductor region laterally surrounding a top portion of the another semiconductor fin that is located above the channel region of the another semiconductor fin.

12. A method of forming a semiconductor structure comprising:
forming a first semiconductor fin extending upwards from a first portion of a doped bottom semiconductor layer and a pair of second semiconductor fins extending from a second portion of the doped bottom semiconductor layer, wherein the first semiconductor fin and the pair of second semiconductor fins are laterally surrounded by a material stack including, from bottom to top, a bottom spacer layer, a sacrificial gate layer, a top spacer layer and a dielectric capping layer, and the pair of second semiconductor fins has a first conductivity type;
removing the dielectric capping layer to exposing a top portion of each of the first semiconductor fin and the pair of the second semiconductor fins located above the top spacer layer;
forming a first doped top semiconductor region laterally surrounding the top portion of the first semiconductor fin and a second doped top semiconductor region laterally surrounding the top portion of each second semiconductor fin;
forming a first sidewall spacer on sidewalls of the first doped top semiconductor region and a second sidewall spacer on sidewalls of each second top semiconductor region;
forming an interlevel dielectric (ILD) layer laterally surrounding the first sidewall spacer and each second sidewall spacer;
removing a portion of the ILD layer located between the adjacent second sidewall spacers to provide an opening exposing a portion of the top spacer layer;
removing the exposed portion of the top spacer layer and a portion of the sacrificial gate layer and a portion of the bottom spacer layer located between the pair of second semiconductor fins to provide a diode trench underneath the opening;
forming a first doped semiconductor segment of the first conductivity type on a surface of the doped bottom semiconductor layer that is exposed by the diode trench; and
forming a second doped semiconductor segment of a second conductivity type opposite to the first conductivity type on the first doped semiconductor segment, wherein the second doped semiconductor segment laterally contacts an inner sidewall of a channel portion of each second semiconductor fin previously covered by the removed portion of the sacrificial gate layer.

13. The method of claim 12 , further comprising forming a top contact segment of the second conductivity type on the second doped semiconductor segment to completely fill the diode trench.

14. The method of claim 13 , further comprising forming an ILD fill portion on the top contact segment, wherein the ILD fill portion completely fills the opening.

15. The method of claim 14 , further comprising removing a portion of the sacrificial gate layer laterally surrounding the first semiconductor fin to expose a channel region of the first semiconductor fin, wherein a portion of the sacrificial gate layer that laterally contacts an outer sidewall of each second semiconductor fin remains.

16. The method of claim 15 , further comprising forming a first metal gate structure laterally surrounding the channel region of the first semiconductor fin.

17. The method of claim 16 , further comprising forming a first transistor contact structure contacting the first metal gate structure, a second transistor contract structure contacting the first doped top semiconductor region, a first diode contact structure contacting the top contact segment, a second diode contact structure contacting each second doped top semiconductor region and a third diode contact structure contacting a portion of the bottom doped semiconductor layer located beneath the portion of the sacrificial gate layer that laterally contacts the outer sidewall of each second semiconductor fin.

18. The method of claim 13 , further comprising removing an entirety of the sacrificial gate layer to expose a channel region of the first semiconductor fin and a channel region of each second semiconductor fin.

19. The method of claim 18 , further comprising forming a first metal gate structure laterally surrounding the channel region of the first semiconductor fin, and a second metal gate structure laterally contacting an outer sidewall of the channel region of each second semiconductor fin.

20. The method of claim 19 , further comprising forming a first transistor contact structure contacting the first metal gate structure, a second transistor contract structure contacting the first doped top semiconductor region, a first diode contact structure contacting the top contact segment and a second diode contact structure contacting each second doped top semiconductor region.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Hashemi Pouya
• Reznicek Alexander
• Yau Jeng-Bang

Classifications

• H01L29/66666

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L27/0255 Primary

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic