Distributed, event-based computation using neuromorphic cores

Patent metadata

Field	Value
Publication number	US-11645501-B2
Application number	US-201815908459-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Feb 28, 2018
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

Systems for distributed, event-based computation are provided. In various embodiments, the systems include a plurality of neurosynaptic processors and a network interconnecting the plurality of neurosynaptic processors. Each neurosynaptic processor includes a clock uncoupled from the clock of each other neurosynaptic processor. Each neurosynaptic processor is adapted to receive an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs. Each neurosynaptic processor is adapted to compute, for each clock value, an output based on the inputs associated with that clock value. Each neurosynaptic processor is adapted to send to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.

First claim

What is claimed is:

1. A system comprising:
a plurality of neurosynaptic processors each of the plurality of neurosynaptic processors including a clock local thereto; and
a network interconnecting the plurality of neurosynaptic processors, wherein
the clock of each neurosynaptic processor is uncoupled from the clock of each other neurosynaptic processor,
each neurosynaptic processor is adapted to receive an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs, wherein the clock value is different from the plurality of inputs and originates at another of the plurality of neurosynaptic processors, each neurosynaptic processor is adapted to compute, for each clock value, an output based on the inputs associated with the clock value, wherein the inputs comprise a neuron state and a vector of axonal inputs, and wherein the output comprises a neuron state associated with a subsequent clock value and a neuron output associated with the subsequent clock value,
each neurosynaptic processor is adapted to send to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.

2. The system of claim 1 , wherein the plurality of neurosynaptic processors comprises at least one neurosynaptic core, neurosynaptic chip, simulated neurosynaptic core, or simulated neurosynaptic chip.

3. The system of claim 1 , wherein the system further comprises:
at least one GPU coupled to the network.

4. The system of claim 3 , wherein the GPU is adapted to encode the plurality of inputs.

5. The system of claim 3 , further comprising an event buffer, the system being adapted to:
route the output and an associated clock value from a first of the neurosynaptic processors to the event buffer;
load a new model to the plurality of neurosynaptic processors; and thereafter provide from the event buffer input to the plurality of neurosynaptic processors.

6. The system of claim 1 , wherein each neurosynaptic processor is configured with a partition of a neural network.

7. The system of claim 6 , wherein the partition is determined by minimizing one or more of total power consumption, total computation time, total network latency, or total communication over the network.

8. The system of claim 1 , wherein the network comprises an Ethernet network.

9. The system of claim 1 , wherein the network comprises a TCP/IP network.

10. The system of claim 1 , wherein each of the plurality of neurosynaptic processors comprises at least one input port and at least one output port.

11. A method comprising:
partitioning a neural network into a plurality of partitions;
determining a communication graph interconnecting the plurality of partitions;
loading each of the plurality of partitions onto one or more neurosynaptic processor;
providing a plurality of network connections interconnecting the plurality of neurosynaptic processors according to the communication graph;
providing a clock local to each neurosynaptic processor, the clock of each neurosynaptic processor being uncoupled from the clock of each other neurosynaptic processor;
at each neurosynaptic processor:
receiving an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs, wherein the clock value is different from the plurality of inputs and originates at another of the plurality of neurosynaptic processors,
computing, for each clock value, an output based on the inputs associated with that clock value, wherein the inputs comprise a neuron state and a vector of axonal inputs, and wherein the output comprises a neuron state associated with a subsequent clock value and a neuron output associated with the subsequent clock value, and
sending to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.

12. The method of claim 11 , wherein the one or more neurosynaptic processor comprises at least one neurosynaptic core, neurosynaptic chip, simulated neurosynaptic core, or simulated neurosynaptic chip.

13. The method of claim 11 , further comprising:
encoding the input stream by at least one GPU.

14. The method of claim 11 , further comprising:
routing the output and an associated clock value from a first of the neurosynaptic processors to an event buffer;
loading a new model to the plurality of neurosynaptic processors; and thereafter providing from the event buffer input to the plurality of neurosynaptic processors.

15. The method of claim 11 , further comprising:
configuring each neurosynaptic processor with a partition of the neural network.

16. The method of claim 15 , further comprising:
determining the partition by minimizing one or more of total power consumption, total computation time, total network latency, or total communication over the network.

17. The method of claim 11 , wherein the network comprises an Ethernet network.

18. The method of claim 11 , wherein the network comprises a TCP/IP network.

19. The method of claim 11 , wherein each of the one or more neurosynaptic processor comprises at least one input port and at least one output port.

20. A computer program product for distributed, event-based computation, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
partitioning a neural network into a plurality of partitions;
determining a communication graph interconnecting the plurality of partitions;
loading each of the plurality of partitions onto one or more neurosynaptic processor;
providing a plurality of network connections interconnecting the plurality of neurosynaptic processors according to the communication graph;
providing a clock local to each neurosynaptic processor, the clock of each neurosynaptic processor being uncoupled from the clock of each other neurosynaptic processor;
at each neurosynaptic processor:
receiving an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs, wherein the clock value is different from the plurality of inputs and originates at another of the plurality of neurosynaptic processors,
computing, for each clock value, an output based on the inputs associated with that clock value, wherein the inputs comprise a neuron state and a vector of axonal inputs, and wherein the output comprises a neuron state associated with a subsequent clock value and a neuron output associated with the subsequent clock value, and
sending to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.

21. The computer program product of claim 20 , wherein the one or more neurosynaptic processor comprises at least one neurosynaptic core, neurosynaptic chip, simulated neurosynaptic core, or simulated neurosynaptic chip.

22. The computer program product of claim 20 , the method further comprising:
encoding the input stream by at least one GPU.

23. The computer program product of claim 20 , the method further comprising:
routing the output and an associated clock value from a first of the neurosynaptic processors to an event buffer;
loading a new model to the plurality of neurosynaptic processors; and thereafter providing from th

Assignees

• IBM

Inventors

• Amir Arnon
• Berg David
• Datta Pallab
• Kusnitz Jeffrey A
• Penner Hartmut

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N20/00

  Machine learning · CPC title

• G06N3/065

  Analogue means · CPC title

• G06N3/045

  Combinations of networks · CPC title