Elementary network description for neuromorphic systems with plurality of doublets wherein doublet events rules are executed in parallel

Patent metadata

Field	Value
Publication number	US-9104973-B2
Application number	US-201113239123-A
Country	US
Kind code	B2
Filing date	Sep 21, 2011
Priority date	Sep 21, 2011
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Neuronal network and methods for operating neuronal networks comprise a plurality of units, where each unit has a memory and a plurality of doublets, each doublet being connected to a pair of the plurality of units. Execution of unit update rules for the plurality of units is order-independent and execution of doublet event rules for the plurality of doublets is order-independent.

First claim

What is claimed is:

1. A system configured to provide a neuronal network, the system comprising:
one or more integrated circuits having a neuronal network embodied therein, the neuronal network comprising:
a plurality of units, each having a memory updated according to a unit update rule; and
a plurality of doublets, each doublet being connected to a pair of the plurality of units and configured to update the memory of a postsynaptic one of the pair of units in response to an event received from the presynaptic other of the pair of units according to a doublet event rule;
wherein execution of unit update rules for the plurality of units is order-independent and execution of doublet event rules for the plurality of doublets is order-independent;
wherein the doublet event rules are executable in parallel; and
wherein the unit update rules are executable in parallel.

2. The system of claim 1 , wherein for the each doublet, the execution of the corresponding doublet event rule is triggered in response to a change in the memory of the presynaptic unit.

3. The system of claim 2 wherein, for at least one doublet, there is a delay between occurrence of changes in the memory of its corresponding presynaptic unit and updates to the memory of its corresponding postsynaptic unit.

4. The system of claim 2 , wherein the doublet event rule for each doublet is triggered when its corresponding presynaptic unit transmits an event to the each doublet.

5. The system of claim 1 , wherein each doublet has a memory that is updated in response to events received from its corresponding presynaptic unit, and wherein the memory of the postsynaptic unit corresponding to the each doublet is updated based on the content of the memory of the each doublet.

6. The system of claim 5 , wherein updates to unit memories and doublet memories are performed within a period of a time determined by a system clock, and wherein all of the updates are completed before the period of time expires.

7. The system of claim 5 , wherein the doublet event rule for each doublet includes a timing event rule that controls modification of the memory of the each doublet.

8. The system of claim 7 , wherein the timing event rule comprises pre-post event rule that controls modification of memory of the each doublet and that depends on the difference between the timing of events transmitted by the presynaptic unit and the timing of at least one subsequent event transmitted by the postsynaptic unit.

9. The system of claim 7 , wherein the timing event rule comprises post-pre event rule that controls modification of memory of the each doublet and that depends on the difference between the timing of events transmitted by the presynaptic unit and the timing of at least one preceding pulse transmitted by the postsynaptic unit.

10. The system of claim 5 , wherein each doublet is configured to update its memory according to a predefined post event rule that is triggered by its corresponding postsynaptic unit.

11. The system of claim 10 , wherein the post event rule depends on the difference between the timing of pulse of the postsynaptic unit and the timing of at least one preceding pulse of the presynaptic unit.

12. The system of claim 1 , wherein the memory of each unit is updated by atomic addition.

13. The system of claim 1 , wherein the neuronal network further comprises a plurality of triplets each having a memory, each triplet being configured to access the memory of two of the plurality of units, wherein each triplet is operable to update its own triplet memory and the memory at least one of the two units in accordance with a triplet rule, wherein execution of triplet update rules for the plurality of triplets is order-independent.

14. The system of claim 13 , wherein the neuronal network is represented as a directed graph.

15. The system of claim 14 , wherein the representation of a neuronal network is mapped to the interconnected plurality of units independently of the physical and electrical structure of the units, the doublets and the triplets.

16. The system of claim 15 , wherein the neuronal network is expressed in a specification provided in non-transitory storage and coded according to a hardware description language.

17. The system of claim 16 , wherein the specification is operable to reconfigure a semiconductor integrated circuit.

18. A method of implementing neuronal networks embodied in one or more integrated circuits, the method comprising:
interconnecting a plurality of units embodied in one or more integrated circuits using doublets configured to modify a memory of a postsynaptic unit responsive to an event received from a presynaptic unit;
configuring doublet event rules that determine how the doublets respond to events; and
configuring a unit update rule for each unit that controls the response of the each unit to memory updates initiated by a doublet, wherein execution of the doublet event rules is order-independent and execution of the unit update rules is order-independent;
wherein configuring doublet event rules includes configuring each of the doublet event rules to be executed within a time step having a duration determined by a system clock after receiving an event during the time step.

19. The method of claim 18 , wherein each presynaptic unit maintains an event condition that controls transmission of events to a doublet.

20. The method of claim 18 , further comprising configuring an after-event unit update rule for each presynaptic unit to be executed in association with the transmission of the events, wherein the after-event unit update rule causes modification of memory of the each presynaptic unit.

21. The method of claim 18 , wherein each doublet modifies the memory of the postsynaptic unit memory by atomic addition.

22. The method of claim 18 , wherein the doublet event rule for each doublet includes a timing event rule that controls modification of a memory of the each doublet based on timing of pulses associated with one or more of the plurality of units.

23. The method of claim 22 , wherein the timing event rule comprises pre-post event rule that controls modification of memory of the each doublet and that depends on the difference between the timing of pulses of a presynaptic unit and the timing of pulses of at least one subsequent pulse of the postsynaptic unit.

24. The method of claim 22 , wherein the timing event rule comprises post-pre event rule that controls modification of memory of the each doublet and that depends on the difference between the timing of pulses of the presynaptic unit and the timing of pulses of at least one preceding pulse of the postsynaptic unit.

25. The method of claim 22 , wherein execution of the doublet event rule for each doublet is triggered by an event received from a presynaptic unit.

26. The method of claim 18 , further comprising
interconnecting a second plurality of units using triplets configured to access memory of a pair of triplet-connected units; and
configuring a triplet update rule for each triplets that controls updates to the memory of the each triplets and the memory of at least one of its corresponding pair of triplet-connected units, wherein execution of triplet update rules is order-independent.

27. The method of claim 26 , wherein the update rule for each triplet responds to information maintained in memories of the pair of units connected by th

Assignees

• Izhikevich Eugene M
• Szatmary Botond
• Petre Csaba
• Nageswaran Jayram Moorkanikara
• Piekniewski Filip
• Qualcomm Technologies Inc

Inventors

• Izhikevich Eugene M
• Szatmary Botond
• Petre Csaba
• Nageswaran Jayram Moorkanikara
• Piekniewski Filip

Classifications

• G06N3/0454

  Physics · mapped topic

• G06N99/007

  Molecular computers, i.e. using inorganic molecules (using biomolecules G06N3/002) · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/105

  Shells for specifying net layout · CPC title