Neuromorphic event-driven neural computing architecture in a scalable neural network

Patent metadata

Field	Value
Publication number	US-9269044-B2
Application number	US-201213585010-A
Country	US
Kind code	B2
Filing date	Aug 14, 2012
Priority date	Sep 16, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

First claim

What is claimed is:

1. A method for event delivery in a neural network including multiple core circuits, wherein each core circuit comprises an electronic synapse array comprising multiple digital synapses interconnecting a plurality of digital electronic neurons such that each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, the method comprising:
in each core circuit:
integrating at least one input spike in a digital electronic neuron of the core circuit;
determining whether the at least one integrated input spike exceeds a threshold of the digital electronic neuron;
in response to determining the at least one integrated input spike exceeds the threshold of the digital electronic neuron, generating an outgoing spike event for delivery to a target axon in an electronic synapse array of the core circuit or another electronic synapse array of another core circuit, wherein the spike event includes a corresponding timestamp indicating generation of the spike event; and
receiving at least one incoming spike event and scheduling delivery of the at least one incoming spike event to at least one target axon in the electronic synapse array of the core circuit, wherein delivery of each incoming spike event is scheduled based on a schedule for deterministic event delivery and a corresponding timestamp for the incoming spike event.

2. The method of claim 1 , wherein scheduling delivery of the at least one incoming spike event comprises delivering each incoming spike event to a target axon in the electronic synapse array of the core circuit after a delay period.

3. The method of claim 2 , wherein the delay period is based on a corresponding timestamp for the incoming spike event and a predetermined delay for event delivery.

4. The method of claim 1 , wherein scheduling delivery of the at least one incoming spike event comprises selectively imposing a delay on delivery of each incoming spike event.

5. The method of claim 1 , wherein scheduling delivery of the at least one incoming spike event comprises delivering each incoming spike event with the same propagation period from event generation.

6. The method of claim 1 , further comprising:
in each core circuit:
routing an outgoing spiking event from a spiking neuron of the core circuit to a target axon in an electronic synapse array of the core circuit or another electronic synapse array of another core circuit utilizing an event router.

7. The method of claim 6 , wherein the event router interconnects at least two core circuits of the multiple core circuits.

8. The method of claim 7 , further comprising:
routing spike events between the multiple core circuits using a plurality of event routers.

9. A system comprising a computer processor, a computer-readable hardware storage device, and program code embodied with the computer-readable hardware storage device for execution by the computer processor to implement a method for event delivery in a neural network including multiple core circuits, wherein each core circuit comprises an electronic synapse array comprising multiple digital synapses interconnecting a plurality of digital electronic neurons such that each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, the method comprising:
in each core circuit:
integrating at least one input spike in a digital electronic neuron of the core circuit;
determining whether the at least one integrated input spike exceeds a threshold of the digital electronic neuron;
in response to determining the at least one integrated input spike exceeds the threshold of the digital electronic neuron, generating an outgoing spike event for delivery to a target axon in an electronic synapse array of the core circuit or another electronic synapse array of another core circuit, wherein the spike event includes a corresponding timestamp indicating generation of the spike event; and
receiving at least one incoming spike event and scheduling delivery of the at least one incoming spike event to at least one target axon in the electronic synapse array of the core circuit, wherein delivery of each incoming spike event is scheduled based on a schedule for deterministic event delivery and a corresponding timestamp for the incoming spike event.

10. The system of claim 9 , wherein scheduling delivery of the at least one incoming spike event comprises delivering each incoming spike event to a target axon in the electronic synapse array of the core circuit after a delay period.

11. The system of claim 10 , wherein the delay period is based on a corresponding timestamp for the incoming spike event and a predetermined delay for event delivery.

12. The system of claim 9 , wherein scheduling delivery of the at least one incoming spike event comprises selectively imposing a delay on delivery of each incoming spike event.

13. The system of claim 9 , wherein scheduling delivery of the at least one incoming spike event comprises delivering each incoming spike event with the same propagation period from event generation.

14. The system of claim 9 , further comprising:
in each core circuit:
routing an outgoing spiking event from a spiking neuron of the core circuit to a target axon in an electronic synapse array of the core circuit or another electronic synapse array of another core circuit utilizing an event router.

15. The system of claim 14 , wherein the event router interconnects at least two core circuits of the multiple core circuits.

16. The system of claim 15 , further comprising:
routing spike events between the multiple core circuits using a plurality of event routers.

17. A computer program product comprising a computer-readable hardware storage device having program code embodied therewith, the program code being executable by a computer to implement a method for event delivery in a neural network including multiple core circuits, wherein each core circuit comprises an electronic synapse array comprising multiple digital synapses interconnecting a plurality of digital electronic neurons such that each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, the method comprising:
in each core circuit:
integrating at least one input spike in a digital electronic neuron of the core circuit;
determining whether the at least one integrated input spike exceeds a threshold of the digital electronic neuron;
in response to determining the at least one integrated input spike exceeds the threshold of the digital electronic neuron, generating an outgoing spike event for delivery to a target axon in an electronic synapse array of the core circuit or another electronic synapse array of another core circuit, wherein the spike event includes a corresponding timestamp indicating generation of the spike event; and
receiving at least one incoming spike event and scheduling delivery of the at least one incoming spike event to at least one target axon in the electronic synapse array of the core circuit, wherein delivery of each incoming spike event is scheduled based on a schedule for deterministic event delivery and a corresponding timestamp for the incoming spike event.

18. The computer program product of claim 17 , wherein scheduling delivery of the at least one incoming spike event comprises delivering each incoming spike event to a target axon in the electronic synapse array of the core circuit after a delay period.

19. The computer program product of claim 18 , wherein the delay period is base

Assignees

• Akopyan Filipp
• Arthur John V
• Manohar Rajit
• Merolla Paul A
• Modha Dharmendra S
• Molnar Alyosha
• Risk Iii William P
• IBM
• Univ Cornell

Inventors

• Akopyan Filipp
• Arthur John V
• Manohar Rajit
• Merolla Paul A
• Modha Dharmendra S
• Molnar Alyosha
• Risk Iii William P

Classifications

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/06 Primary

  Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/082

  modifying the architecture, e.g. adding, deleting or silencing nodes or connections · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title