Hardware apparatuses and methods for memory corruption detection

Patent metadata

Field	Value
Publication number	US-11645135-B2
Application number	US-202017020663-A
Country	US
Kind code	B2
Filing date	Sep 14, 2020
Priority date	Dec 21, 2015
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

First claim

What is claimed is:

1. A processor comprising:
decode circuitry to decode a load instruction, the load instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [59:56]; and
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
determine whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data;
load the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory; and
generate a fault when the 4-bit value from the 64-bit pointer does not match the 4-bit value from the memory.

2. The processor of claim 1 , wherein the 64-bit pointer is to indicate whether the circuitry is to determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory corresponding to the 128-bit block of data.

3. The processor of claim 1 , wherein a value in the 64-bit pointer is to indicate whether the circuitry is to determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory corresponding to the 128-bit block of data.

4. The processor of claim 1 , wherein the processor is to access the 4-bit value from the memory with an address that lacks the 4-bit value from the 64-bit pointer.

5. The processor of claim 1 , wherein the processor is to access the 4-bit value from the memory with an address that has either all zeroes or all ones in bits [59:56].

6. The processor of claim 1 , wherein, in addition to the 4-bit value from the bits [59:56], the processor is also to protect the 64-bit pointer based on another value from the 64-bit pointer.

7. The processor of claim 1 , wherein the 4-bit value from the memory is from a table in the memory, the table to have a plurality of 4-bit values respectively corresponding to different ones of a plurality of 128-bit blocks of data in the memory.

8. The processor of claim 7 , wherein the table is stored separately from the 128-bit blocks of data.

9. The processor of claim 1 , wherein the 4-bit value from the 64-bit pointer is a memory corruption detection (MCD) value.

10. The processor of claim 1 , further comprising a register to control whether the circuitry is to determine whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data.

11. The processor of claim 1 , wherein the processor is a general-purpose CPU core, the general-purpose CPU core further comprising:
a branch prediction circuitry;
a register rename circuitry; and
scheduler circuitry.

12. The processor of claim 1 , wherein the processor is a reduced instruction set computing (RISC) processor.

13. A method comprising:
decoding a load instruction, the load instruction operating on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [59:56]; and
based on the decode of the load instruction:
determining whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data;
loading the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory; and
generating a fault when the 4-bit value from the 64-bit pointer does not match the 4-bit value from the memory.

14. The method of claim 13 , further comprising determining from the 64-bit pointer whether to perform said determining whether the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory corresponding to the 128-bit block of data.

15. The method of claim 13 , further comprising determining from a value in the 64-bit pointer whether to perform said determining whether the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory corresponding to the 128-bit block of data.

16. The method of claim 13 , further comprising accessing the 4-bit value from the memory with an address that lacks the 4-bit value from the 64-bit pointer.

17. The method of claim 13 , further comprising accessing the 4-bit value from the memory with an address that has either all zeroes or all ones in bits [59:56].

18. The method of claim 13 , further comprising, in addition to protecting the 64-bit pointer with the 4-bit value from the bits [59:56], also protecting the 64-bit pointer based on another value from the 64-bit pointer.

19. The method of claim 13 , further comprising accessing the 4-bit value from a table in the memory, the table having a plurality of 4-bit values respectively corresponding to different ones of a plurality of 128-bit blocks of data in the memory, and wherein the table is stored separately from the 128-bit blocks of data.

20. A processor comprising:
decode circuitry to decode a load instruction, the load instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [59:56];
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
determine from the 64-bit pointer that the circuitry is to determine whether the 4-bit value from the 64-bit pointer matches a 4-bit value corresponding to the 128-bit block of data from the memory;
access the 4-bit value from the memory with an address that lacks the 4-bit value from the 64-bit pointer;
determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory;
load the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory; and
generate a fault when the 4-bit value from the 64-bit pointer does not match the 4-bit value from the memory.

21. The processor of claim 20 , wherein the circuitry is to determine from a value in the 64-bit pointer that the circuitry is to determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory.

22. The processor of claim 21 , wherein the circuitry is to access the 4-bit value from a table in the memory, the table to have a plurality of 4-bit values respectively corresponding to different ones of a plurality of 128-bit blocks of data in the memory, and wherein the table is stored separately from the 128-bit blocks of data.

23. The processor of claim 21 , wherein, in addition to protecting the 64-bit pointer based on the 4-bit value from the bits [59:56], the processor is also to protect the 64-bit pointer based on another value from the 64-bit pointer.

24. A computer system comprising:
a dynamic random access memory (DRAM); and
a processor coupled with the DRAM, the processor comprising:
decode circuitry to decode a load instruction, the load instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [59:56]; and
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
determine whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data;
load the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value from

Assignees

• Intel Corp

Inventors

• Stark Tomer
• Gabor Ron
• Nuzman Joseph
• Sade Raanan
• Bigbee Bryant E

Classifications

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/656

  Address space sharing · CPC title

• G06F2212/1052

  Security improvement · CPC title