Byte level granularity buffer overflow detection for memory corruption detection architectures

Patent metadata

Field	Value
Publication number	US-2016283300-A1
Application number	US-201514668862-A
Country	US
Kind code	A1
Filing date	Mar 25, 2015
Priority date	Mar 2, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.

First claim

What is claimed is:

1 . A processor comprising:
a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table and a memory object; and a processor core coupled to the memory, wherein the processing core is to:
receive, from the application, a memory access request to access data of the memory object with a contiguous memory block in a memory object of the memory, wherein the memory access request comprises:
a pointer indicating a location in the memory of the memory object; and
a first MCD unique identifier (ID);

retrieve data stored in the contiguous memory block based on the location indicated by the pointer;
retrieve, from the MCD table, allocation information associated with the contiguous memory block, wherein the allocation information comprises:
a second MCD unique identifier associated with the contiguous memory block; and
a MCD border value indicating a size of a first memory region of the contiguous memory block; and

send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.

2 . The processor of claim 1 , wherein:
the contiguous memory block comprises a usable memory region and an unusable memory region; and the first memory region is the usable memory region or the unusable memory region.

3 . The processor of claim 2 , wherein the processing core is further to:
compare the first MCD unique ID to the second MCD unique ID to determine when the retrieved data is from the memory object indicated by the pointer; and determine when the retrieved data is from the usable memory region based on the allocation information.

4 . The processor of claim 3 , wherein the fault event occurs when:
the first MCD unique ID does not match the second MCD unique ID; or the memory access is within the unusable memory region.

5 . The processor of claim 2 , wherein the processing core is further to determine the usable memory region by:
subtracting the MCD border value from a size value of the contiguous memory block to obtain a border location value; and identifying a MCD border location in the contiguous memory block based on border location value, wherein the MCD border location indicates a boundary between the usable memory region and the unusable memory region.

6 . The processor of claim 5 , wherein the size of the contiguous memory block is 64 bytes.

7 . The processor of claim 2 , wherein the entire contiguous memory block is the usable memory region when the MCD border value is zero.

8 . A processor, comprising:
a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table; and a processor core coupled to the memory, wherein the processing core is to:
receive, from the application, an allocation request for an allocation of a memory object with one or more contiguous memory blocks in the memory;
allocate the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested, wherein a contiguous memory block of the one or more contiguous memory blocks comprise a first memory region and a second memory region; and
write, into the MCD table, a MCD meta-data word, wherein the MCD meta-data word comprises:
a first MCD unique identifier associated with the contiguous memory block; and
a MCD border value indicating a size of the first memory region of the contiguous memory block.

9 . The processor of claim 8 , wherein the first memory region is a used portion of the contiguous memory block.

10 . The processor of claim 8 , wherein the first memory region is an unused portion of the contiguous memory block.

11 . The processor of claim 8 , wherein the processor core is further to:
create a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object; and send, to the application, the pointer.

12 . The processor of claim 8 , wherein the contiguous memory block is 64 bytes in size.

13 . The processor of claim 8 , wherein the MCD meta-data word is 2 bytes in size, and wherein:
the MCD unique ID is 1 byte of the MCD meta-data word, and the MCD border value is 1 byte of the MCD meta-data word.

14 . A system on a chip (SoC) comprising:
a processor; a memory device, coupled to the processor, to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table and a memory object; and a memory controller coupled to the memory device, the memory controller to:
receive, from the application, a memory access request to access data of the memory object with a contiguous memory block, wherein the memory access request comprises:
a pointer indicating a location in the memory of the memory object; and
a first MCD unique identifier (ID);

retrieve data stored in the contiguous memory block based on the location indicated by the pointer;
retrieve, from the MCD table, allocation information associated with the contiguous memory block, wherein the allocation information comprises:
a second MCD unique identifier associated with the contiguous memory block; and
a MCD border value indicating a size of a first memory region of the contiguous memory block; and

determine when the retrieved data is from a usable region of memory based on the allocation information; and
send, to the application, the retrieved data.

15 . The SoC claim of claim 14 , wherein:
the contiguous memory block comprises a usable memory region and an unusable memory region; and the first memory region is the usable memory region or the unusable memory region.

16 . The SoC claim of claim 15 , wherein the entire contiguous memory block is the usable memory region when the MCD border value is zero.

17 . The SoC claim of claim 15 , wherein the memory controller is further to compare the first MCD unique ID to the second MCD unique ID to determine when the retrieved data is from the memory object indicated by the pointer.

18 . The SoC claim of claim 17 , wherein the memory controller is further to send, to the application, a fault message when a fault event associated with the retrieved data occurs, wherein the fault event occurs when:
the first MCD unique ID does not match the second MCD unique ID; or the memory access is within the unusable memory region.

19 . The SoC claim of claim 15 , wherein the memory controller is further to determine the usable memory region by:
subtracting the MCD border value from a size value of the contiguous memory block to obtain a border location value; and identifying a MCD border location in the contiguous memory block based on border location value, wherein the MCD border location indicates a boundary between the usable memory region and the unusable memory region.

20 . The SoC claim of claim 19 , wherein the size of the contiguous memory block is 64 bytes.

Assignees

• Intel Corp

Inventors

• Stark Tomer
• Tal Ady
• Gabor Ron
• Nuzman Joseph

Classifications

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title