Heap management for memory corruption detection

Patent metadata

Field	Value
Publication number	US-2016259682-A1
Application number	US-201514635896-A
Country	US
Kind code	A1
Filing date	Mar 2, 2015
Priority date	Mar 2, 2015
Publication date	Sep 8, 2016
Grant date	—

Abstract

Memory corruption detection technologies are described. A method can include receiving, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object. The method can further include allocating, by a processor, the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested. The method can further include writing, into a MCD table, a first memory corruption detection (MCD) unique identifier associated with the one or more contiguous memory blocks. The method can further include creating a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object. The method can further include sending, to the application, the pointer.

First claim

What is claimed is:

1 . A processor, comprising:
a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table; and a processor core coupled to the memory, wherein the processing core is operable to:
receive, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object;
allocate the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested;
write, into the MCD table, a first MCD unique identifier associated with the one or more contiguous memory blocks;
create a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object; and
send, to the application, the pointer.

2 . The processor of claim 1 , wherein the processor core is further to determine the size of the memory object requested by the allocation request.

3 . The processor of claim 1 , wherein the processor core is further to:
compare the first MCD unique identifier with the second MCD unique identifier; and communicate a corruption detection message to the application when the first MCD unique identifier and the second MCD unique identifier do not match.

4 . The processor of claim 1 , wherein the size of the memory object requested is:
a first size, wherein the first size is a request for the memory object with a number of contiguous memory blocks below a first threshold amount; a second size, wherein the second size is a request for the memory object with a number of contiguous memory blocks that exceeds the first threshold amount and is below a second threshold amount; and a third size, wherein the third size is a request for the memory object with a number of contiguous memory blocks that exceeds the second threshold amount.

5 . The processor of claim 1 , wherein the processor core is further to:
divide the one or more contiguous memory blocks into a plurality of sub-blocks, wherein the plurality of sub-blocks comprise:
an initial sub-block;
one or more middle sub-blocks; and
a last sub-block; and
store data, to be aligned with to each of the plurality of sub-blocks, of at least one of a memory allocation meta-data field, a user data field, an overhead data filed, or an empty data field.

6 . The processor of claim 5 , wherein the processor core is further to:
store data of the memory allocation meta-data field within initial sub-block so that the memory allocation meta-data field is aligned with a starting boundary of the initial block; store data of the user data field within a first middle sub-block of the one or more middle sub-blocks so that the user data field is aligned with a starting boundary of the first middle sub-block; and store data of the overhead data field with the last sub-block of the last sub-block so that the overhead data field is aligned with an ending boundary of the last sub-block.

7 . The processor of claim 5 , the processor core is further to:
store data of the empty data field within initial sub-block so that the empty data field is aligned with a starting boundary of the initial block; store data of the memory allocation meta-data field within a first middle sub-block of the one or more middle sub-blocks so that the memory allocation meta-data field is aligned with a starting boundary of the first middle sub-block; store data of the user data field within a second middle sub-block of the one or more middle sub-blocks so that the user data field is aligned with a starting boundary of the second middle sub-block; and store data of the overhead data field with the last sub-block of the last sub-block so that the overhead data field is aligned with an ending boundary of the last sub-block.

8 . The processor of claim 5 , the processor core is further to:
store data of the memory allocation meta-data field within initial sub-block so that the memory allocation meta-data field is aligned with a starting boundary of the initial block; store data of the overhead data field within a first middle sub-block of the one or more middle sub-blocks so that the overhead data field is aligned with a starting boundary of the first middle sub-block; and store data of the user data field with the last sub-block of the last sub-block so that the user data field is aligned with an ending boundary of the last sub-block.

9 . The processor of claim 5 , wherein the processor core is further to store data of the memory allocation meta-data field, data of the user data field, data of the overhead data field, or data of the empty data field based on a predetermined sub-block alignment of the processor.

10 . The processor of claim 1 , wherein the processor is further to determine the MCD unique identifier associated with the memory object using a round-robin selection scheme.

11 . The processor of claim 1 , wherein the processor core is further to:
determine the MCD unique identifier associated with the memory object using a random selection scheme; and verify that the MCD unique identifier is different from another MCD unique identifier of an adjacent contiguous memory block.

12 . A system on a chip (SoC) comprising:
a processor; a memory device coupled to the processor; a memory controller coupled to the memory device, the memory controller to:
receive, from an application, an release request for a release of a memory object in a system memory of a processor, wherein the release request comprises a pointer;
identify a first memory corruption detection (MCD) unique identifier and a memory address of the pointer;
change the first MCD unique identifier;
change a second MCD unique identifier in a MCD table of the system memory associated with the memory address of the pointer; and
release a memory object in the system memory associated with the memory address.

13 . The SoC claim 12 , wherein the memory controller is further to change, by the processor device, the second MCD unique identifier using a round-robin selection scheme.

14 . The SoC claim 12 , wherein the memory controller is further to change, by the processor device, the second MCD unique identifier using a random selection scheme.

15 . The SoC claim 14 , wherein the memory controller is further to verifying, by the processor device, that the second MCD unique identifier is different from another MCD unique identifier of an adjacent contiguous memory block.

16 . A method comprising:
receiving, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object; allocating, by a processor, the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested; writing, into a MCD table, a first memory corruption detection (MCD) unique identifier associated with the one or more contiguous memory blocks; creating a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object; and sending, to the application, the pointer.

17 . The method of claim 16 , further comprising determining, by the processor the size of the memory object requested by the allocation request.

18 . The method of claim 16 , further comprising:
comparing the first MCD unique identifier with the second MCD unique identifier; and communicating a corruption detection message to the application when the first MCD unique identifier the second MCD unique identifier do not match.

Assignees

• Intel Corp

Inventors

• Stark Tomer
• Tal Ady
• Gabor Ron

Classifications

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/1064 Primary

  in cache or content addressable memories · CPC title