Multiple chunk support for memory corruption detection architectures

Patent metadata

Field	Value
Publication number	US-2016371179-A1
Application number	US-201514746702-A
Country	US
Kind code	A1
Filing date	Jun 22, 2015
Priority date	Jun 22, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

Memory corruption detection technologies are described. An example processing system includes a processing core including a register to store an address of a memory corruption detection (MCD) table. The processing core can allocate a memory block of pre-determined size and can allocate a plurality of buffers within the memory block using a memory metadata word stored in an entry of the MCD table. The memory metadata word can include metadata that can identify a first bit range within the memory block for a first buffer and a second bit range within the memory block for a second buffer

First claim

What is claimed is:

1 . A processing system comprising:
a processing core comprising a register to store an address of a memory corruption detection (MCD) table, wherein the processing core is to allocate a memory block of pre-determined size and to allocate a plurality of buffers within the memory block using a memory metadata word stored in an entry of the MCD table, wherein the memory metadata word comprises metadata to identify a first bit range within the memory block for a first buffer and a second bit range within the memory block for a second buffer.

2 . The processing system of claim 1 , wherein the processor core is to allocate the plurality of buffers by setting an indicator bit within the memory metadata word.

3 . The processing system of claim 1 , wherein each of the plurality of buffers is protected by a corresponding unique MCD color code defined by the memory metadata word stored in the MCD table.

4 . The processing system of claim 3 , wherein the processor core is to return a failure in response to a determination that an MCD color code of a pointer conflicts with a MCD color code corresponding to first buffer.

5 . The processing system of claim 1 , wherein the processor core is to access the first buffer using the memory metadata word stored in the entry of the MCD table and to access the second buffer using the memory metadata word stored in the same entry of the MCD table.

6 . The processing system of claim 1 , wherein the processing system comprises a system-on-a-chip (SoC).

7 . The processing system of claim 1 , wherein the first buffer of the plurality of buffers is aligned to a first position within the memory block and the second buffer of the plurality of buffers is aligned to a second position within the memory block, wherein the first position is different from the second position.

8 . The processing system of claim 1 , wherein the processing core is to change one or more portions of the memory metadata word corresponding to one or more of the plurality of buffers within the memory block in response to a deallocation request.

9 . A method comprising:
allocating a first memory chunk within a memory block, the memory blocking having of pre-determined size; generating a memory corruption detection (MCD) metadata word associated with the first memory chunk; setting an indicator bit within the MCD metadata word to indicate a multiple chunk support state; setting a pointer color code associated with the first memory chunk; and verifying an access request to the first memory chunk by checking the pointer color code against the memory metadata word associated with the first memory chunk.

10 . The method of claim 9 , further comprising returning a failure in response to a determination that the pointer color code conflicts with a color code of the MCD metadata word.

11 . The method of claim 9 , wherein the memory metadata word corresponds with the memory block.

12 . The method of claim 9 , further comprising allocating a portion of memory to which to store an MCD table in response to a request to initialize the MCD table.

13 . The method of claim 9 , further comprising allocating a second memory chunk, wherein the first memory chunk is aligned to a first position within the memory block and the second memory chunk is aligned to a second position within the memory block.

14 . The method of claim 13 , wherein the memory metadata word comprises MCD values corresponding to both the first memory buffer and the second memory buffer.

15 . A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processor, cause the processor to:
allocate a first memory chunk within a memory block of pre-determined size; initialize a memory corruption detection (MCD) table; generate a first MCD metadata word associated with the first memory chunk; set an indicator bit within the MCD metadata word to indicate a multiple chunk support state; initialize, based on the MCD metadata word, a first MCD table entry corresponding to the memory block; and generate a first pointer to reference the first memory chunk, wherein the pointer comprises a first bit sequence, derived from the MCD metadata word, within a pre-defined bit position of the first pointer associated with the first memory chunk.

16 . The computer-readable non-transitory storage medium of claim 15 , further comprising executable instructions that, when executed by a processor, cause the processor to:
allocate a second memory chunk to the memory block; generate a second MCD value corresponding to the second memory chunk; initialize a second MCD table entry corresponding to the memory block, wherein the second MCD table entry is based on the second MCD value; update the MCD metadata word attached to the memory block to correspond with the second memory chunk; and generate a second pointer to reference the second memory chunk, wherein the second pointer comprises a second bit sequence associating the second pointer with the second memory chunk.

17 . The computer-readable non-transitory storage medium of claim 16 , wherein the first memory chunk is aligned to a first position within the memory block and the second memory chunk is aligned to a second position within the memory block.

18 . The computer-readable non-transitory storage medium of claim 15 , further comprising executable instructions that, when executed by a processor, cause the processor to validate an application pointer generated by a first memory chunk access request of an application by comparing with the application pointer with the first MCD value stored in the MDC table.

19 . The computer-readable non-transitory storage medium of claim 17 , further comprising executable instructions that, when executed by a processor, cause the processor to return a failure in response to a determination that the first pointer conflicts with the MCD table entry corresponding to the first memory chunk.

20 . The computer-readable non-transitory storage medium of claim 15 , further comprising executable instructions that, when executed by a processor, cause the processor to change one or more portions of the MCD metadata word attached to the memory block in response to a deallocation request.

Assignees

• Intel Corp

Inventors

• Stark Tomer
• Gabor Ron
• Nuzman Joseph

Classifications

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/023 Primary

  Free address space management · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/0775

  Content or structure details of the error report, e.g. specific table structure, specific error fields · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title