Memory device with a multi-mode communication mechanism

Patent metadata

Field	Value
Publication number	US-11637903-B2
Application number	US-202217698952-A
Country	US
Kind code	B2
Filing date	Mar 18, 2022
Priority date	Aug 23, 2017
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

A memory device includes a communication circuit configured to communicate a first signal and a second signal; and a selection mechanism coupled to the communication circuit and configured to select between operating the communication circuit the first signal and the second signal (1) independent signals for separate memory operations or (2) a complementary set for a memory operation.

First claim

We claim:

1. A memory device, comprising:
a communication circuit including
a first external interface configured to send or receive a first signal, and
a second external interface configured to send or receive a second signal; and

a selection mechanism coupled to the communication circuit and configured to operate the communication circuit in sending or receiving the first signal and the second signal (1) as independent signals corresponding to separate memory operations or (2) as a contemporaneous set corresponding to a memory operation.

2. The memory device of claim 1 , wherein the first signal and the second signal are complementary signals when sending or receiving as the contemporaneous set.

3. The memory device of claim 2 , wherein the first signal and the second signal are a differential pair.

4. The memory device of claim 3 , wherein the first and second signals as the independent signals implement Open NAND Flash Interface (ONFI) communication.

5. The memory device of claim 1 , wherein the selection mechanism includes at least two switches that are configured to operate according to a selection to communicate the first and second signals as the independent signals or the complementary set.

6. The memory device of claim 5 , wherein the communication circuit includes:
a first transmitter configured to send a first output stream; and
a second transmitter configurable to send a second output stream.

7. The memory device of claim 6 , wherein the selection mechanism includes an inverter and is configured to send the first and second signals as the contemporaneous set by:
providing the first output stream to the inverter,
providing an output of the inverter to the first external interface as the first signal;
activating a first of the at least two switches to route the first output stream to the second external interface to send the second signal; and
operating a second of the at least two switches to isolate the second transmitter from the first and second external interfaces.

8. The memory device of claim 7 , wherein the selection mechanism and/or the communication circuit are configured to deactivate the second transmitter based on a selection to communicate the complementary set.

9. The memory device of claim 6 , wherein the selection mechanism is configured to send the first and second signals as the independent signals by:
operating a first of the at least two switches to isolate the first transmitter and the second transmitter from each other; and
operating a second of the at least two switches to connect the second transmitter to the second external interface;
wherein
the first transmitter is coupled to the first external interface.

10. The memory device of claim 6 , wherein the set of switches are arranged according to an H-bridge configuration and is configured to selectively operate the first and second transmitters as a differential pair.

11. The memory device of claim 5 , wherein the communicating circuit includes:
a first receiver configured to receive the first signal, wherein the first receiver includes a first reference connection; and
a second receiver configured to receive the second signal, wherein the second receiver includes a second reference connection.

12. The memory device of claim 11 , wherein the selection mechanism is configured to receive the first and second signals as the contemporaneous set by operating the at least two switches to:
route the second signal from the second external interface to the first reference portion for using the second signal as reference in detecting the first signal, wherein
the first signal from the first external interface is provided as input to the first detector; and

isolate the first reference portion from electrical ground.

13. The memory device of claim 11 , wherein the selection mechanism is configured to receive the first and second signals as the independent signals by operating the at least two switches to:
connect respective reference portions of the first receiver and the second receiver to an electrical ground for communicating the independent signals;
isolate the first receiver from the second signal from the second external interface; and
isolate the second receiver from the first signal from the first external interface;
wherein
the first and second signals are provided as inputs to first and second receivers, respectively.

14. The memory device of claim 1 , wherein the communication circuit is configured to implement bidirectional communication between a memory array and a controller of the memory device.

15. The memory device of claim 1 wherein the communication circuit is included in a controller, a memory array, a host device, or a combination thereof.

16. A memory device, comprising:
a memory array; and
a controller configured to communicate a first signal and a second signal between the memory array and the controller;
wherein the memory array and/or the controller include
a communication circuit having
a first set of external interfaces at the memory array and the controller for exchanging the first signal, and
a second set of external interfaces at the memory array and the controller for exchanging the second signal; and

a selection mechanism configured to operate the communication circuit or a portion thereof in exchanging the first and second signals (1) as independent signals corresponding to separate memory operations or (2) as a contemporaneous set corresponding to a memory operation.

17. The memory device of claim 16 , wherein the selection mechanism is configured to operate the communication circuit or a portion thereof to communicate the first and second signals as complementary signals when sending or receiving as the contemporaneous set.

18. The memory device of claim 17 , wherein the first and second signals are communicated as a differential pair when sending or receiving as the contemporaneous set.

19. The memory device of claim 16 wherein the communication circuit is configured to implement bidirectional communication between the memory array and the controller.

20. The memory device of claim 16 wherein the selection mechanism is configured to implement the independent communication mode based on communicating the first and second signals according to an Open NAND Flash Interface (ONFI).

Assignees

• Micron Technology Inc

Inventors

• Rowley Matthew D
• Bauer Mark

Classifications

• H04L67/567

  Integrating service provisioning from a plurality of service providers · CPC title

• H04L67/2885 Primary

  Hierarchically arranged intermediate devices, e.g. for hierarchical caching · CPC title

• H04W88/16

  Gateway arrangements · CPC title

• H04L69/18

  Multiprotocol handlers, e.g. single devices capable of handling multiple protocols · CPC title

• H04W88/06

  adapted for operation in multiple networks {or having at least two operational modes}, e.g. multi-mode terminals · CPC title