Virtual container storage interface controller
US-12175078-B2 · Dec 24, 2024 · US
Clock mode determination in a memory system
US2016293265A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016293265-A1 |
| Application number | US-201615183162-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 15, 2016 |
| Priority date | Feb 16, 2007 |
| Publication date | Oct 6, 2016 |
| Grant date | — |
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- Title
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- Abstract
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Abstract
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A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device for receiving a clock and input data comprising: a configurable input circuit operable in a first mode for receiving coincident edges of the clock and the input data, and for providing shifted clock edges positioned within a data valid window for sampling the input data, the configurable input circuit being operable in a second mode for receiving non-coincident edges of the clock and the input data for sampling the input data.
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Classifications
Clock input buffers · CPC title
- G06F3/061Primary
Improving I/O performance · CPC title
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title
comprising cells having several storage transistors connected in series · CPC title
using counters · CPC title
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- What does patent US2016293265A1 cover?
- A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circu…
- Who is the assignee on this patent?
- Conversant Intellectual Property Man Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F3/061. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Oct 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).