Control arrangements and methods for accessing block oriented nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9489302-B2
Application number	US-201514721841-A
Country	US
Kind code	B2
Filing date	May 26, 2015
Priority date	Feb 2, 2011
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes at least one module including a nonvolatile memory section that is made up of a plurality of memory devices and the module includes a bit density function to assign a storage density to each memory device such that one group of the memory devices is configured to store data at a high storage density and another group of the memory devices is configured to store data at a low storage density. The module independently performs the bit density function for the nonvolatile memory section of each module based on one or more module input parameters.

First claim

What is claimed is:

1. A memory system for digital data communication with a host device to provide data storage capacity for the host device, said memory system comprising:
at least one module including a nonvolatile memory section that is made up of a plurality of memory devices that are distinct from one another and the module includes a bit density function to assign a storage density to each memory device such that one group of the memory devices is configured to store data at a high storage density and another group of the memory devices is configured to store data at a low storage density, where the high storage density is greater than the low storage density, and the module independently performs the bit density setting function for the nonvolatile memory section of only that module based on one or more module input parameters; and
a controller configured for said digital data communication with the host device and further configured for module digital data communication with the module such that any data flowing to and from the module passes through the controller.

2. The memory system of claim 1 wherein each memory device is made up of a plurality of memory cells and the high storage density is more than two bits per cell while the low storage density is no more than two bits per cell.

3. The memory system of claim 1 wherein the controller is configured to provide the module input parameters to the module to define an independent execution of the bit density function by the module.

4. The memory system of claim 1 wherein the module is configured to generate the module input parameters to define an independent execution of the bit density function by the module.

5. The memory system of claim 1 wherein the controller is configured to provide one set of module input parameters to the module and the module is configured to generate another set of input parameters and the module is configured to apply precedence to the set module input parameters, as generated by the controller, to define an independent execution of the bit density function by the module.

6. The memory system of claim 1 wherein the controller is configured to provide a first set of module input parameters to the module and the module is configured to generate another a second set of input parameters and the module is configured to use a combination of the first set of module input parameters and the second set of module input parameters to define an independent execution of the bit density function by the module.

7. The memory system of claim 1 wherein the storage density, as assigned, is based on memory capability data for the module.

8. The memory system of claim 7 wherein the memory capability data is based, at least in part, on a signal to noise ratio of the nonvolatile memory section.

9. The memory system of claim 8 wherein the memory capability data is based, at least in part, on a use history of the nonvolatile memory section.

10. The memory system of claim 1 wherein the nonvolatile memory is block oriented and wherein the module is configured to independently perform the bit density function by assigning the storage density to the nonvolatile memory at least down to a block level.

11. The memory system of claim 10 wherein the module is configured to assign the storage density based on a bit density configuration menu.

12. The memory system of claim 11 wherein the bit density configuration includes a predefined set of bit density configurations.

13. The memory system of claim 12 wherein each bit density configuration represents an overall combination of said module input parameters.

14. The memory system of claim 13 wherein each parameter defines at least the number of bits in a memory cell, encoding/decoding parameters and an amount of parity.

15. The memory system of claim 1 wherein the bit density function is configured to monitor the nonvolatile memory section for physical degradation.

16. The memory system of claim 15 wherein the bit density function monitors physical degradation of the nonvolatile memory section based on a signal to noise ratio.

17. The memory system of claim 1 wherein said module input parameters are based, at least in part, on memory capacity, density and lifetime of the nonvolatile memory section.

18. A module for use in a memory system for digital data communication with a host device to provide data storage capacity for the host device, said module comprising:
a nonvolatile memory section that is made up of a plurality of memory devices that are distinct from one another;
a bit density function to assign a storage density to each memory device such that one group of the memory devices is configured to store data at a high storage density and another group of the memory devices is configured to store data at a low storage density, where the high storage density is greater than the low storage density, and the module independently performs the bit density setting function for the nonvolatile memory section of only that module based on one or more module input parameters for interfacing with a controller that is configured for said digital data communication with the host device; and
the module is further configured for module digital data communication with the controller module such that any data flowing to and from the module passes through the controller.

19. A method for controlling a memory system for digital data communication with a host device to provide data storage capacity for the host device, said method comprising:
in at least one module which forms part of the memory system and which includes a nonvolatile memory section that is made up of a plurality of memory devices that are distinct from one another, independently executing a bit density function for the nonvolatile memory section of only that module based on one or more module input parameters to assign a storage density to each memory device such that one group of the memory devices is configured to store data at a high storage density and another group of the memory devices is configured to store data at a low storage density, where the high storage density is greater than the low storage density.

Assignees

• Micron Technology Inc

Inventors

• Van Aken Stephen P

Classifications

• G06F2212/7205

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• G06F2212/1028

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• G06F2212/7211

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• G06F2212/7207

  management of metadata or control data · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title