Electrical connector with high speed mounting interface

Patent metadata

Field	Value
Publication number	US-11637403-B2
Application number	US-202117159855-A
Country	US
Kind code	B2
Filing date	Jan 27, 2021
Priority date	Jan 27, 2020
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

An electrical interconnect for passing high speed signals through an electronic system with a high density of signals and high signal integrity. The interconnect includes an electrical connector and a transition portion of a printed circuit board to which the connector is mounted. Signal conductors are connected to pads on the surface of the PCB using edge-to-pad mounting. The pads align with intermediate portions of the signal conductors such that transitions within the connector that could degrade signal integrity are avoided. The signal conductors may be positioned as individually shielded broadside coupled pairs extending in rows within the connector. Surface traces on the PCB connect the pads to signal vias aligned for vertical routing out of the connector footprint. Ground planes underlying the surface traces facilitate a transition from the signal paths in the connector to those in the PCB with low mode conversion avoiding resonances in the connector shields.

First claim

What is claimed is:

1. A substrate, comprising:
an insulative layer comprising a surface;
a pair of signal vias;
a pair of signal contact pads disposed on the surface, wherein contact pads of the pair are spaced from one another along a first line; and
conductive traces disposed on the surface and electrically coupling respective contact pads of the pair of contact pads and signal vias of the pair of signal vias,
wherein signal vias of the pair of signal vias are spaced from one another along a second line disposed at an angle of at least 45 degrees with respect to the first line.

2. The substrate of claim 1 , wherein the angle is 90 degrees.

3. The substrate of claim 1 , wherein:
the substrate further comprises a ground plane on the surface, the ground plane comprising an opening;
the pair of signal contact pads and the pair of signal vias are within the opening; and
the substrate further comprises a plurality of ground vias electrically coupled to the ground plane.

4. The substrate of claim 3 , wherein the ground vias have a drilled diameter of less than 16 mils.

5. The substrate of claim 3 , wherein the ground plane comprises a plurality of portions exposed for physically contacting a ground structure of a connector mounted to the substrate.

6. The substrate of claim 1 , wherein the signal vias have a drilled diameter of less than 10 mils.

7. The substrate of claim 1 , wherein the signal vias have a drilled diameter between 7 and 9 mils.

8. The substrate of claim 1 , wherein the signal contact pads have a diameter between 10 and 14 mils.

9. A substrate comprising a connector footprint, wherein the connector footprint comprises a plurality of regions disposed in rows and columns, each region comprising:
a pair of signal vias, wherein signal vias of the pair are separated from one another along a first direction;
a pair of conductive pads, wherein conductive pads of the pair are separated from one another along a second direction that is orthogonal to the first direction; and
conductive traces interconnecting respective ones of the signal vias and conductive pads.

10. The substrate of claim 9 , further comprising:
routing channels extending in the first direction between pairs of signal vias in adjacent columns.

11. The substrate of claim 10 , wherein each region further comprises:
a plurality of ground vias.

12. The substrate of claim 10 , further comprising an edge, wherein:
the connector footprint is adjacent the edge; and
the first direction is perpendicular to the edge.

13. The substrate of claim 9 , wherein:
each region of the plurality of regions has an area of less than 2.5 mm 2 .

14. The substrate of claim 9 , wherein:
regions of the plurality of regions are separated, center-to-center, in the first direction by less than 2.5 mm.

15. The substrate of claim 9 , wherein:
regions of the plurality of regions are separated, center-to-center, in the second direction by less than 2.5 mm.

16. An electronic assembly comprising:
a substrate comprising a plurality of conductive pads on a surface of the substrate and a plurality of vias, wherein the conductive pads are connected to signal traces within the substrate and the vias are connected to ground structures within the substrate; and
a connector mounted to the substrate, wherein:
the connector comprises a plurality of signal conductors and a plurality of shielding members at least partially surrounding subsets of the plurality of signal conductors;
the signal conductors comprise contact tails comprising broad sides and edges and the edges are facing and connected to respective ones of the plurality of conductive pads;
the plurality of shielding members comprise contact tails inserted within respective vias of the plurality of vias.

17. The electronic assembly of claim 16 , wherein:
the contact tails are connected to respective ones of the plurality of conductive pads with soldered butt joints.

18. The electronic assembly of claim 16 , wherein:
the contact tails are connected to respective ones of the plurality of conductive pads with a pressure mount connection.

19. The substrate of claim 3 , wherein the plurality of ground vias comprises a first ground via having a first drilled diameter and a second ground via having a second drilled diameter different from the first drilled diameter.

20. The substrate of claim 19 , wherein the first ground via is exposed for physically contacting a ground structure of a connector mounted to the substrate.

21. The substrate of claim 19 , wherein the second ground via is spaced from the pair of signal contact pads along the first line.

22. The substrate of claim 19 , wherein the second ground via is spaced from the pair of signal vias along the second line.

23. The substrate of claim 3 , wherein:
the pair of signal contact pads, the conductive traces, and the ground plane comprise a first conductive layer of the substrate;
the ground plane is a first ground plane; and
the substrate further comprises a second conductive layer comprising a second ground plane that is electrically coupled to the first ground plane by the plurality of ground vias.

24. The substrate of claim 23 , further comprising a third conductive layer comprising a plurality of conductive traces electrically coupled to respective ones of the conductive traces of the first conductive layer by the pair of signal vias, wherein the pair of signal vias extend from the first conductive layer to the third conductive layer through the second conductive layer.

25. The substrate of claim 24 , further comprising:
an electrical connector comprising a pair of broadside coupled signal conductors coupled to the pair of signal contact pads,
wherein:
the conductive traces on the third conductive layer connected to the pair of signal vias are edge coupled; and
the substrate and electrical connector are configured such that differential signals are coupled between the signal conductors of the connector and the conductive traces on the third conductive layer with less than −40 dB of suck out loss over the frequency range of 56 GHz to 112 GHz.

26. The substrate of claim 24 , further comprising a pair of un-plated holes extending from the first conductive layer toward the third conductive layer and concentric with the pair of signal vias.

27. The substrate of claim 11 , further comprising a first ground via disposed between a first region and a second region of the plurality of regions.

28. The substrate of claim 27 , wherein the first ground via is disposed between the first and second regions in the row direction, and the substrate further comprises a second via disposed between the first region and a third region of the plurality of regions in the column direction.

29. The substrate of claim 28 , wherein the plurality of ground vias of each region have a first drilled diameter and the first and second ground vias have drilled diameters that are smaller than the first drilled diameter.

30. The electronic assembly of claim 16 , wherein the substrate further comprises a first auxiliary via disposed between a first pair of the signal conductors and a second pair of the signal conductors of the connector in a first direction separating the broad sides of the first pair of the signal conductors.

31. The electron

Assignees

• Amphenol Corp

Inventors

• Cartier Jr Marc B
• Dunham John Robert
• Gailus Mark W
• Levine David
• Astbury Allan
• Sivarajan Vysakh
• Provencher Daniel B
• Leo Eric

Classifications

• H05K1/114

  Pad being close to via, but not surrounding the via · CPC title

• H05K1/0219

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H05K1/0222

  for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence · CPC title

• H05K1/0218

  by printed shielding conductors, ground planes or power plane (H05K1/0236 takes precedence) · CPC title

• H01R13/6585

  Shielding material individually surrounding or interposed between mutually spaced contacts · CPC title