Gate-all-around structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11637207-B2
Application number	US-202117175816-A
Country	US
Kind code	B2
Filing date	Feb 15, 2021
Priority date	Nov 27, 2018
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

First claim

What is claimed is:

1. A device comprising:
a fin protruding from a substrate and disposed between portions of an isolation structure;
a semiconductor layer over the fin;
a gate dielectric wrapping around the semiconductor layer;
a gate electrode wrapping around the gate dielectric disposed on the semiconductor layer;
a source/drain feature interfacing with the semiconductor layer; and
a dielectric inner spacer having a first portion disposed between the source/drain feature and a portion of the gate electrode and a second portion between the source/drain feature and the substrate, wherein the second portion of the dielectric inner spacer has a top surface in direct contact with a bottom surface of the source/drain feature.

2. The device of claim 1 , further comprising:
a fin dielectric layer extending from the substrate along a sidewall of the fin, the fin dielectric layer contacting the dielectric inner spacer and the isolation structure.

3. The device of claim 1 , wherein the semiconductor layer includes a top surface facing away from the substrate and a bottom surface facing the substrate, and
wherein the first portion of the dielectric inner spacer physically contacts the top surface of the semiconductor layer and the second portion of the dielectric inner spacer physically contacts the bottom surface of the semiconductor layer.

4. The device of claim 1 , wherein the semiconductor layer has a first thickness adjacent the source/drain feature and a second thickness positioned further away from the source/drain feature, the second thickness being different than the first thickness.

5. The device of claim 4 , wherein the gate dielectric wraps around a first portion of the semiconductor layer having the second thickness without wrapping around a second portion of the semiconductor layer having the first thickness.

6. The device of claim 1 , wherein the dielectric inner spacer is formed of an oxide material.

7. A device comprising:
a first plurality of semiconductor layers disposed over a first portion of a semiconductor fin protruding from a substrate;
a second plurality of semiconductor layers disposed over a second portion of the semiconductor fin protruding from the substrate;
a first gate dielectric layer wrapping around at least one semiconductor layer from the first plurality of semiconductor layers;
a first gate electrode wrapping around the first gate dielectric layer disposed on the at least one semiconductor layer from the first plurality of semiconductor layers;
a source/drain feature interfacing with the at least one semiconductor layer from the first plurality of semiconductor layers; and
a dielectric inner spacer including a first portion extending from the at least one semiconductor layer from the first plurality of semiconductor layers to one of the semiconductor layer from the second plurality of semiconductor layers,
wherein the dielectric inner spacer covers a top surface of the source/drain feature.

8. The device of claim 7 , wherein each semiconductor layer from the first plurality of semiconductor layers is spaced apart from each other, and
wherein each semiconductor layer from the second plurality of semiconductor layers is spaced apart from each other.

9. The device of claim 7 , wherein the first plurality of semiconductor layers is formed of a same material, and
wherein the second plurality of semiconductor layers is formed of the same material.

10. The device of claim 7 , further comprising:
a second gate dielectric layer wrapping around at least one semiconductor layer from the second plurality of semiconductor layers; and
a second gate electrode wrapping around the second gate dielectric layer disposed on the at least one semiconductor layer from the second plurality of semiconductor layers, and
wherein a second portion of the dielectric inner spacer extends from the first gate electrode to the second gate electrode.

11. The device of claim 7 , wherein the first portion of the dielectric inner spacer further extends under the source/drain feature.

12. The device of claim 7 , wherein the source/drain feature further interfaces with at least one semiconductor layer from the second plurality of semiconductor layers.

13. The device of claim 7 , further comprising a shallow trench isolation structure disposed on the substrate, the shallow trench isolation structure having a top surface facing away from the substrate,
wherein the first and second portions of the semiconductor fin extend through the shallow trench isolation structure,
wherein a top surface of the first portion of the semiconductor fin is positioned below the top surface of the shallow trench isolation structure, the top surface of the first portion of the semiconductor fin facing towards the first plurality of semiconductor layers, and
wherein a second portion of the dielectric inner spacer is disposed directly on the top surface of the first portion of the semiconductor fin such that the second portion of the dielectric inner spacer is positioned below the top surface of the shallow trench isolation structure.

14. A method comprising:
forming a fin over a substrate, wherein the fin includes a plurality of semiconductor layers disposed over a channel region and a source/drain region of the substrate;
removing a portion of the fin in the source/drain region of the substrate to form a trench therein;
selectively removing portions from at least one of semiconductor layer from the plurality of semiconductor layers in the channel region of the substrate to form at least one recessed semiconductor layer in the channel region;
forming a material layer directly on the at least one recessed semiconductor layer and in the trench;
forming a source/drain feature on the material layer disposed in the trench; and
after forming the source/drain feature, converting the material layer to a dielectric material layer.

15. The method of claim 14 , wherein the converting of the material layer to the dielectric material layer includes:
removing the material layer from the at least one recessed semiconductor layer and the trench; and
forming the dielectric material layer directly on the at least one recessed semiconductor layer and in the trench.

16. The method of claim 14 , wherein the converting of the material layer to the dielectric material layer includes performing an oxidation process on the material layer to thereby form the dielectric material layer.

17. The method of claim 14 , further comprising:
after the converting of the material layer to the dielectric material layer, forming a gate dielectric layer on the at least one recessed semiconductor layer; and
forming a gate electrode layer on the gate dielectric layer.

18. The method of claim 14 , further comprising removing at least one semiconductor layer from the plurality of semiconductor layers in the channel region of the substrate after the converting of the material layer to the dielectric material layer.

19. The method of claim 14 , wherein the material layer includes an element selected from the group consisting of Si, Ge and C.

20. The device of claim 1 , further comprising another semiconductor layer disposed over the fin, the semiconductor layer disposed on a first side of the source/drain feature and the another semiconductor layer disposed on a second side of the source/drain feature, the second side of the source/drain feature being opposite the first side of the source/drain feature, and
wherein the dielectric inner spacer exten

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Pei-Hsun
• Lin Chun-Hsiung
• Wang Chih-Hao

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title