Silicon-containing layer for bit line resistance reduction

Patent metadata

Field	Value
Publication number	US-11637107-B2
Application number	US-202117351223-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	Jun 17, 2021
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

First claim

What is claimed is:

1. A bit line stack comprising:
a polysilicon layer;
an adhesion layer on the polysilicon layer;
a barrier metal layer on the adhesion layer;
an interface layer on the barrier metal layer;
a silicon oxide resistance reducing layer directly on the interface layer; and
a conductive layer over the silicon oxide resistance reducing layer.

2. The bit line stack of claim 1 , wherein the silicon oxide resistance reducing layer has a thickness in a range of from 2 Å to 30 Å.

3. The bit line stack of claim 1 , wherein the adhesion layer comprises one or more of titanium (Ti), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi) or cobalt silicide (CoSi).

4. The bit line stack of claim 3 , wherein the adhesion layer comprises titanium.

5. The bit line stack of claim 4 , wherein the adhesion layer has a thickness in a range of from 10 Å to 30 Å.

6. The bit line stack of claim 1 , wherein the barrier metal layer comprises tungsten nitride.

7. The bit line stack of claim 6 , wherein the barrier metal layer has a thickness in a range of from 10 Å to 30 Å.

8. The bit line stack of claim 1 , wherein the interface layer comprises one or more of tungsten silicide (WSi) or tungsten silicon nitride (WSiN).

9. The bit line stack of claim 1 , wherein the interface layer has a thickness in a range of from 10 Å to 30 Å.

10. The bit line stack of claim 1 , wherein the conductive layer comprises one or more of tungsten (W), ruthenium (Ru), iridium (Jr), molybdenum (Mo), platinum (Pt) or rhodium (Rh).

11. The bit line stack of claim 1 , wherein the conductive layer has a thickness greater than or equal to 50 Å.

12. The bit line stack of claim 1 , wherein the bit line stack has a resistance at least 5% lower than a comparable bit line stack without the silicon oxide resistance reducing layer.

Assignees

• Applied Materials Inc

Inventors

• Yu Tom Ho Wing
• Sasaki Nobuyuki
• Lei Jianxin
• Hou Wenting
• Wang Rongjun
• Gung Tza-Jing

Classifications

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/31

  having a storage electrode stacked over the transistor · CPC title

• H10B12/482 Primary

  Bit lines · CPC title

• H01L27/10885 Primary

  Electricity · mapped topic

• H01L27/10805

  Electricity · mapped topic