Dynamic random access memory and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9947669-B1
Application number	US-201715590023-A
Country	US
Kind code	B1
Filing date	May 9, 2017
Priority date	May 9, 2017
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A dynamic random access memory (DRAM) includes a substrate, a plurality of isolation structures, a plurality of conductive structure sets, a plurality of bit-line structures, and a plurality of spacers. The substrate has a plurality of active areas. The isolation structures are located in the substrate and extending along a first direction. Each of the isolation structures is disposed between two adjacent active areas. The conductive structure sets are disposed in parallel along the first direction and on the substrate. The bit-line structures are disposed in parallel along a second direction and on the substrate. The bit-line structures penetrate through the conductive structure sets. The spacers are disposed in parallel along the second direction and on sidewalls of the bit-line structures, so as to electrically isolate the bit-line structures from the conductive structure sets.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) comprising:
a substrate having a plurality of active areas that are configured into a strip and arranged as an array;
a plurality of isolation structures located in the substrate and extending along a first direction, wherein each of the isolation structures is disposed between two adjacent active areas;
a plurality of conductive structure sets disposed in parallel along the first direction and on the substrate, wherein each of the conductive structure sets is connected to each of the active areas arranged in the same column, so as to form a first contact region and a second contact region on each of the active areas;
a plurality of bit-line structures disposed in parallel along a second direction and on the substrate, wherein the bit-line structures penetrate through the conductive structure sets and each of the bit-line structures is connected to portions of the active areas arranged in the same column, so as to form a third contact region between the first contact region and the second contact region; and
a plurality of spacers disposed in parallel along the second direction and on sidewalls of the bit-line structures, so as to electrically isolate the bit-line structures from the conductive structure sets.

2. The DRAM according to claim 1 , further comprising a plurality of word line sets located in the substrate and extending along the first direction, wherein each of the word line sets has two buried word lines, and the third contact regions of the active areas arranged in the same column are sandwiched by the two buried word lines.

3. The DRAM according to claim 2 , wherein each of the bit-line structures comprises a bit-line contact, a bit line, and a cap layer, the bit-line contact located between the bit line and the third contact region, so as to electrically connect the bit line and the third contact region.

4. The DRAM according to claim 3 , wherein the bit-line contacts comprise polysilicon layers, epitaxial silicon layers, or a combination thereof.

5. The DRAM according to claim 1 , wherein the spacers comprise single-layer structures, two-layer structures, or multi-layer structures.

6. The DRAM according to claim 1 , wherein each of the spacers comprises silicon oxide, air gap, silicon nitride, or a combination thereof.

7. The DRAM according to claim 1 , wherein a top width of each of the bit-line structures is substantial equal to a bottom width of each of the bit-line structures.

8. The DRAM according to claim 7 , wherein a width of each of the bit-line structures is less than a width at a short side of each of the active areas.

9. The DRAM according to claim 1 , wherein the conductive structure sets being in contact with the first contact regions and the second contact regions are capacitor contacts.

10. The DRAM according to claim 9 , wherein each of the capacitor contacts comprises poly-Si, SiGe, SiC or a combination thereof.

11. The DRAM according to claim 1 , wherein the active areas in two adjacent columns are arranged in a mirrored configuration.

12. The DRAM according to claim 11 , wherein an angle is between a direction extending along long sides of the active areas and the second direction, the angle is non-orthogonal.

13. A method of manufacturing a dynamic random access memory (DRAM) comprising:
providing a substrate having a plurality of active areas that are configured into a strip and arranged as an array;
forming a plurality of isolation structures located in the substrate and extending along a first direction, wherein each of the isolation structures is disposed between two adjacent active areas;
forming a plurality of conductive structure sets disposed in parallel along the first direction and on the substrate, wherein each of the conductive structure sets is connected to each of the active areas arranged in the same column, so as to form a first contact region and a second contact region on each of the active areas;
forming a plurality of openings extending along a second direction, wherein portions of the active areas are exposed by the openings;
forming a plurality of spacers on sidewalls of the openings, wherein the spacers are extending along the second direction; and
forming a plurality of bit-line structures between the spacers in the openings, wherein each of the bit-line structures is connected to the portions of the active areas arranged in the same column, so as to form a third contact region between the first contact region and the second contact region.

14. The method of manufacturing the DRAM according to claim 13 , before forming the openings, the method further comprising forming a dielectric layer on the conductive structure sets, wherein the dielectric layer is filled in spaces between the conductive structure sets, so that the openings penetrate through in the dielectric layer and the conductive structure sets.

15. The method of manufacturing the DRAM according to claim 13 , wherein each of the bit-line structures comprises a bit-line contact, a bit line, and a cap layer, the bit-line contact located between the bit line and the third contact region, so as to electrically connect the bit line and the third contact region.

16. The method of manufacturing the DRAM according to claim 15 , wherein a forming method of the bit-line contacts comprises a chemical vapor deposition (CVD) process, a selective epitaxial growth (SEG) process, or a combination thereof.

17. The method of manufacturing the DRAM according to claim 13 , wherein the spacers comprise single-layer structures, two-layer structures, or multi-layer structures.

18. The method of manufacturing the DRAM according to claim 13 , wherein each of the spacers comprises silicon oxide, air gap, silicon nitride, or a combination thereof.

19. The method of manufacturing the DRAM according to claim 13 , wherein the conductive structure sets being in contact with the first contact regions and the second contact regions are capacitor contacts.

20. The method of manufacturing the DRAM according to claim 13 , further comprising forming a plurality of word line sets located in the substrate and extending along the first direction, wherein each of the word line sets has two buried word lines, and the third contact regions of the active areas arranged in the same column are sandwiched by the two buried word lines.

Assignees

• Winbond Electronics Corp

Inventors

• Takesako Kazuaki
• Tanaka Yoshinori

Classifications

• H01L27/10885

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L27/108

  Electricity · mapped topic