Semiconductor device

Patent metadata

Field	Value
Publication number	US-11626499-B2
Application number	US-202117524259-A
Country	US
Kind code	B2
Filing date	Nov 11, 2021
Priority date	Jun 25, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.

First claim

What is claimed is:

1. A semiconductor device comprising: a substrate including an active region; an active pattern on the active region of the substrate, the active pattern including a first channel pattern and a first source/drain pattern connected to the first channel pattern; a first gate electrode on the first channel pattern; a first contact structure on the first source/drain pattern and electrically connected to the first source/drain pattern; and a gate contact on the first gate electrode and electrically connected to the first gate electrode, wherein the first contact structure includes: a first lower contact electrically connected to the first source/drain pattern; and an upper insulation layer on the first lower contact, wherein the gate contact vertically overlaps the first channel pattern, wherein the upper insulation layer is adjacent to the gate contact, wherein a top surface of the first lower contact is lower than a bottom surface of the gate contact, and wherein the active pattern comprises vertically protruding portions.

2. The semiconductor device of claim 1 , wherein the upper insulation layer covers the top surface of the first lower contact.

3. The semiconductor device of claim 1 , further comprising:
a first via on the gate contact; and
a first wiring line electrically connected to the gate contact through the first via.

4. The semiconductor device of claim 1 , wherein the active pattern further includes a second channel pattern and a second source/drain pattern connected to the second channel pattern,
wherein the semiconductor device further comprises:
a second gate electrode on the second channel pattern; and
a second contact structure on the second source/drain pattern and electrically connected to the second source/drain pattern,
wherein the second contact structure includes:
a second lower contact that is electrically connected to the second source/drain pattern; and
an upper contact on a top surface of the second lower contact, and
wherein the upper contact vertically overlaps the second source/drain pattern.

5. The semiconductor device of claim 4 , further comprising:
a second via on the upper contact; and
a second wiring line electrically connected to the second contact structure through the second via.

6. The semiconductor device of claim 4 , wherein a width of the upper contact is less than a width of the second lower contact.

7. The semiconductor device of claim 1 , wherein the first lower contact is spaced part from the gate contact by the upper insulation layer.

8. The semiconductor device of claim 1 , wherein the first contact structure further includes a contact spacer on a sidewall of the first lower contact and a sidewall of the upper insulation layer.

9. The semiconductor device of claim 1 , wherein the first contact structure further includes a contact spacer on a sidewall of the first lower contact and a sidewall of the upper insulation layer.

10. The semiconductor device of claim 1 , wherein the top surface of the first lower contact is lower than a top surface of the first gate electrode.

11. A semiconductor device comprising: a substrate; a first active pattern on the substrate; a second active pattern on the substrate; a device isolation layer on the substrate, the device isolation layer being between the first active pattern and the second active pattern; a first source/drain pattern on the first active pattern; a second source/drain on the second active pattern; and a contact structure on at least one of the first and second source/drain patterns, wherein the contact structure includes: a lower contact electrically connected to the at least one of the first and second source/drain patterns; an upper contact on the lower contact; and an upper insulation layer on the lower contact, wherein the upper insulation layer covers a sidewall of the upper contact, wherein the lower contact includes a conductive pattern and a barrier pattern on side and bottom surfaces of the conductive pattern, wherein a top surface of the conductive pattern is at a different level than a top surface of the barrier pattern, wherein the upper insulation layer covers the top surface of the conductive pattern and the top surface of the barrier pattern, wherein at least one of the first active pattern and the second active pattern comprises vertically protruding portions.

12. The semiconductor device of claim 11 , wherein a width of the upper contact is less than a width of the lower contact.

13. The semiconductor device of claim 11 , wherein the top surface of the conductive pattern is higher than the top surface of the barrier pattern.

14. The semiconductor device of claim 11 , wherein the top surface of the conductive pattern is lower than the top surface of the barrier pattern.

15. The semiconductor device of claim 11 , wherein the upper contact contains the same material as the conductive pattern.

16. A semiconductor device comprising: a substrate; a first active pattern on the substrate; a second active pattern on the substrate; a device isolation layer on the substrate, the device isolation layer being between the first active pattern and the second active pattern; a first source/drain pattern on the first active pattern; a second source/drain on the second active pattern; and a contact structure on at least one of the first and second source/drain patterns, wherein the contact structure includes: a lower conductive portion electrically connected to the at least one of the first and second source/drain patterns; an upper conductive portion vertically extends from the lower conductive portion; an upper insulation layer fills a recess between the lower conductive portion and an upper conductive portion; and a contact spacer on a sidewall of the lower conductive portion and a sidewall of the upper insulation layer, wherein at least one of the first active pattern and the second active pattern comprises vertically protruding portions.

17. The semiconductor device of claim 16 , wherein the lower conductive portion includes a conductive pattern and a barrier pattern on side and bottom surfaces of the conductive pattern,
wherein a top surface of the conductive pattern is at a different level than a top surface of the barrier pattern, and
wherein the upper insulation layer covers the top surface of the conductive pattern and the top surface of the barrier pattern.

18. The semiconductor device of claim 16 , wherein the upper conductive portion contains the same metal as the lower conductive portion.

19. The semiconductor device of claim 16 , wherein a width of the upper conductive portion is less than a width of the lower conductive portion.

20. The semiconductor device of claim 16 , further comprising:
a via on a top surface of the upper conductive portion; and
a wiring line electrically connected to the contact structure through the via.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Wonkeun
• Lee Heonbok
• Shin Chunghwan
• Chai Youngsuk
• Hyun Sangjin

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title