Back-gate field-effect transistors and methods for making the same

Patent metadata

Field	Value
Publication number	US-11626486-B2
Application number	US-201916966893-A
Country	US
Kind code	B2
Filing date	Jan 29, 2019
Priority date	Jan 29, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (L G ) or contact length (L C ). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6× improvement to EDP compared to top-gate CNFETs.

First claim

The invention claimed is:

1. A transistor comprising:
a substrate;
a dielectric layer disposed on the substrate;
a channel having a first side facing away from the dielectric layer and a second side opposite the first side and disposed on the dielectric layer;
a source disposed on the first side of the channel;
a drain disposed on the first side of the channel and spaced apart from the source by a physical channel length of less than about 10 nm; and
a gate disposed between the substrate and the dielectric layer and having a gate length greater than the physical channel length and a surface extending from the substrate.

2. The transistor of claim 1 , wherein the transistor has a contacted gate pitch of 15 nm to 30 nm.

3. The transistor of claim 1 , wherein the transistor has a parasitic capacitance of less than 0.1 femtofarads/micron.

4. The transistor of claim 1 , wherein the channel comprises a nanotube in electrical communication with the source and the drain.

5. The transistor of claim 4 , further comprising:
a dielectric disposed between the gate and the nanotube.

6. The transistor of claim 1 , wherein the gate overlaps at least one of the source or the drain.

7. The transistor of claim 1 , wherein the transistor is configured to operate at a clock frequency ranging between about 0.1 GHz and about 10 GHz.

8. The transistor of claim 1 , wherein the source extends beyond a first edge of the gate and the drain extends beyond a second edge of the gate opposite the first edge and further comprising:
a source contact in electrical communication with the source; and
a drain contact in electrical communication with the drain.

9. A transistor comprising:
a channel having a first side and a second side opposite the first side;
a source disposed on a first side of the channel;
a drain disposed on the first side of the channel; and
a gate, disposed on the second side of the channel, overlapping at least one of the source or the drain,
wherein the transistor has a contacted gate pitch of 15 nm to 30 nm and a parasitic capacitance of less than 0.1 femtofarads/micron and is configured to operate at an energy per cycle of less than 0.4 pJ at a clock frequency of 7 GHz or higher.

10. The transistor of claim 9 , wherein the channel comprises a nanotube in electrical communication with the source and the drain.

11. The transistor of claim 10 , further comprising:
a dielectric disposed between the gate and the nanotube.

12. The transistor of claim 9 , wherein the transistor is configured to operate at a clock frequency ranging between about 0.1 GHz and about 10 GHz.

13. A method of making a transistor, the method comprising:
forming a gate;
depositing a dielectric on the gate;
depositing a carbon nanotube over the dielectric to form a channel;
patterning one of a source or a drain on the channel opposite the gate; and
after patterning the one of the source or the drain, patterning the other of the source or the drain on the channel opposite the gate with a physical channel length less than a length of the gate and less than about 10 nm.

14. The method of claim 13 , wherein depositing the carbon nanotube occurs at a temperature of less than about 400 degrees Celsius.

15. The method of claim 13 , wherein patterning the one of the source or the drain comprises lithographically etching with the physical channel length at a minimum feature size.

16. The method of claim 13 , wherein patterning the one of the source or the drain comprises overlapping the one of the source or the drain with the gate.

17. The method of claim 13 , further comprising:
before forming the gate, patterning a trench into a substrate such that the gate, when formed, is embedded in the substrate.

18. The method of claim 13 , wherein forming the gate comprises depositing a gate material on a substrate and patterning the gate material.

Assignees

• Massachusetts Inst Technology
• Analog Devices Inc

Inventors

• Shulaker Max
• Srimani Tathagata
• Fuller Samuel
• Stein Yosi
• Murphy Denis

Classifications

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• H10K10/491

  Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs] · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10K85/221

  Carbon nanotubes · CPC title

• H10K10/481

  characterised by the gate conductors · CPC title