Silicon-containing layer for bit line resistance reduction

Patent metadata

Field	Value
Publication number	US-11626410-B2
Application number	US-202217861412-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Jun 17, 2021
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

First claim

What is claimed is:

1. A method of forming a bit line stack, the method comprising:
forming an adhesion layer on a polysilicon layer;
forming a barrier metal layer on the adhesion layer;
forming an interface layer on the barrier metal layer;
forming a silicon oxide resistance reducing layer directly on the interface layer; and
forming a conductive layer over the silicon oxide resistance reducing layer.

2. The method of claim 1 , wherein the silicon oxide resistance reducing layer has a thickness in a range of from 2 Å to 30 Å.

3. The method of claim 1 , wherein the bit line stack has a resistance at least 5% lower than a comparable bit line stack without the silicon oxide resistance reducing layer.

4. The method of claim 1 , wherein the silicon oxide resistance reducing layer is formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

5. The method of claim 4 , wherein the silicon oxide resistance reducing layer is formed using a PVD process comprising a silicon target and an oxygen plasma.

6. The method of claim 4 , wherein the silicon oxide resistance reducing layer is formed using a PVD process comprising a silicon oxide target and a plasma comprising one or more of argon (Ar), krypton (Kr) or neon (Ne).

7. The method of claim 1 , further comprising performing a post-deposition anneal process at a temperature of at least 500° C.

8. The method of claim 1 , wherein the adhesion layer comprises one or more of titanium (Ti), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi) or cobalt silicide (CoSi).

9. The method of claim 8 , wherein the adhesion layer comprises titanium.

10. The method of claim 9 , wherein the adhesion layer has a thickness in a range of from 10 Å to 30 Å.

11. The method of claim 1 , wherein the barrier metal layer comprises tungsten nitride.

12. The method of claim 11 , wherein the barrier metal layer has a thickness in a range of from 10 Å to 30 Å.

13. The method of claim 1 , wherein the interface layer comprises one or more of tungsten silicide (WSi) or tungsten silicon nitride (WSiN).

14. The method of claim 1 , wherein the interface layer has a thickness in a range of from 10 Å to 30 Å.

15. The method of claim 1 , wherein the conductive layer comprises one or more of tungsten (W), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt) or rhodium (Rh).

16. The method of claim 1 , wherein the conductive layer has a thickness greater than or equal to 50 Å.

Assignees

• Applied Materials Inc

Inventors

• Yu Tom Ho Wing
• Sasaki Nobuyuki
• Lei Jianxin
• Hou Wenting
• Wang Rongjun
• Gung Tza-Jing

Classifications

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/31

  having a storage electrode stacked over the transistor · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H01L27/10885 Primary

  Electricity · mapped topic

• H01L27/10805

  Electricity · mapped topic