Interconnect structure with redundant electrical connectors and associated systems and methods

Patent metadata

Field	Value
Publication number	US-11626388-B2
Application number	US-202217580521-A
Country	US
Kind code	B2
Filing date	Jan 20, 2022
Priority date	May 27, 2014
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

First claim

I claim:

1. A semiconductor device, comprising:
a semiconductor substrate;
a conductive trace disposed at a surface of the semiconductor substrate; and
a plurality of redundant electrical connectors electrically coupled to the conductive trace and extending away from the semiconductor substrate.

2. The semiconductor device of claim 1 , further comprising a through-substrate via extend away from the conductive trace into the semiconductor substrate.

3. The semiconductor device of claim 2 , further comprising:
a substrate contact coupled to a portion of the conductive trace and positioned directly between the conductive trace and the through-substrate via.

4. The semiconductor device of claim 1 , wherein the conductive trace is a first conductive trace and the plurality of redundant electrical connectors is a first plurality of redundant electrical connectors, and further comprising:
a second conductive trace; and
a second plurality of redundant electrical connectors electrically coupled to the conductive trace and extending away from the semiconductor substrate.

5. The semiconductor device of claim 4 , wherein the second plurality of redundant electrical connectors extend away from the semiconductor substrate in a different direction than does the first plurality of redundant electrical connectors.

6. The semiconductor device of claim 1 , further comprising:
a dielectric material over the surface of the semiconductor substrate, wherein the conductive trace extends at least partially through the dielectric material.

7. The semiconductor device of claim 6 , wherein the dielectric material includes a plurality of openings exposing portions of the conductive trace, wherein the redundant electrical connectors extend through the openings.

8. The semiconductor device of claim 1 , wherein the plurality of redundant electrical connectors extend from the conductive trace and through a portion of a dielectric material disposed over the surface of the semiconductor substrate.

9. The semiconductor device of claim 1 , wherein each of the redundant electrical connectors includes:
a conductive pillar coupled to the conductive trace, and
a conductive bond material bonded to the conductive pillar.

10. The semiconductor device of claim 9 , wherein the conductive pillar comprises copper and the bond material comprises a solder material.

11. The semiconductor device of claim 9 , wherein the conductive pillar includes an end portion, and wherein the conductive bond material and conductive pillar form a conductive joint at the end portion.

12. The semiconductor device of claim 9 , wherein the conductive pillar includes generally vertical sidewalls and a barrier and/or seed material covering at least a portion of the sidewalls.

13. A semiconductor device, comprising:
a semiconductor substrate;
a patterned conductive film disposed at a surface of the semiconductor substrate; and
a plurality of redundant electrical connectors electrically coupled to the patterned conductive film and extending away from the semiconductor substrate.

14. The semiconductor device of claim 13 , wherein each of the plurality of redundant electrical connectors includes:
a conductive pillar coupled to the patterned conductive film, and
a conductive bond material bonded to the conductive pillar.

15. The semiconductor device of claim 14 , wherein the conductive pillar comprises copper, and the bond material comprises a solder material.

16. The semiconductor device of claim 13 , wherein all of the plurality of redundant electrical connectors are electrically coupled to one another by the patterned conductive film.

17. A semiconductor device, comprising:
a semiconductor substrate;
a conductive structure disposed at a surface of the semiconductor substrate; and
a plurality of redundant electrical connectors electrically coupled to the patterned conductive film and extending away from the semiconductor substrate,
wherein all of the plurality of redundant electrical connectors are electrically coupled to one another by the conductive structure.

18. The semiconductor device of claim 17 , wherein each of the plurality of redundant electrical connectors includes:
a conductive pillar coupled to the conductive structure, and
a conductive bond material bonded to the conductive pillar.

19. The semiconductor device of claim 18 , wherein the conductive pillar comprises copper, and the bond material comprises a solder material.

20. The semiconductor device of claim 18 , wherein the conductive pillar includes generally vertical sidewalls and a barrier and/or seed material covering at least a portion of the sidewalls.

Assignees

• Micron Technology Inc

Inventors

• Chandolu Anilkumar

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title