Interconnect structure with redundant electrical connectors and associated systems and methods

Patent metadata

Field	Value
Publication number	US-10943888-B2
Application number	US-201916257438-A
Country	US
Kind code	B2
Filing date	Jan 25, 2019
Priority date	May 27, 2014
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

First claim

I claim:

1. A semiconductor die assembly, comprising:
a first semiconductor die;
a second semiconductor die; and
an interconnect structure having a first trace coupled to the first semiconductor die and a second trace coupled to the second semiconductor die, the interconnect structure having a plurality of redundant electrical connectors extending between and attached to the first and second traces, the plurality of redundant electrical connectors being electrically coupled to one another via the first trace.

2. The semiconductor die assembly of claim 1 wherein the plurality of redundant electrical connectors include at least one redundant electrical connector that is separated from the second trace.

3. The semiconductor die assembly of claim 1 wherein the plurality of redundant electrical connectors each include:
a conductive member coupled to the first trace; and
a solder material coupled to the conductive member.

4. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die includes a first substrate and a first through-substrate via (TSV) extending through the first substrate, wherein the first TSV is coupled to the first trace; and
the second semiconductor die includes a second substrate and a second TSV extending through the second substrate, wherein the second TSV is coupled to the second trace.

5. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die includes a substrate and a through-substrate via (TSV) extending through the substrate, wherein the TSV is coupled to the first trace.

6. The semiconductor die assembly of claim 5 wherein at least one of the plurality redundant electrical connectors extends between the TSV and the second trace.

7. The semiconductor die assembly of claim 1 wherein each of the first and second traces includes a conductive trace.

8. The semiconductor die assembly of claim 1 wherein the first semiconductor die is a logic die.

9. The semiconductor die assembly of claim 1 wherein the first semiconductor die is a memory die.

10. The semiconductor die assembly of claim 1 wherein the second semiconductor die is a logic die.

11. The semiconductor die assembly of claim 1 wherein the second semiconductor die is a memory die.

12. A semiconductor die assembly, comprising:
a first semiconductor die having a first conductive trace;
a second semiconductor die having a second conductive trace;
a plurality of redundant electrical connectors extending between the first and second conductive traces, each of the redundant electrical connectors being coupled to the first conductive trace and including—
a conductive member coupled to the first conductive trace; and
a conductive bond material between the conductive member and the second conductive trace.

13. The semiconductor die assembly of claim 12 wherein the first semiconductor die is a logic die.

14. The semiconductor die assembly of claim 12 wherein the first semiconductor die is a memory die.

15. The semiconductor die assembly of claim 12 wherein the second semiconductor die is a logic die.

16. The semiconductor die assembly of claim 12 wherein the second semiconductor die is a memory die.

17. A semiconductor die assembly, comprising:
a first semiconductor die having a first conductive trace;
a second semiconductor die having a second conductive trace;
a plurality of redundant electrical connectors extending between the first and second conductive traces, each of the plurality of redundant electrical connectors including a conductive member coupled to the first conductive trace; and
a conductive bond material between the conductive member and the second conductive trace.

18. The semiconductor die assembly of claim 17 wherein the conductive bond material of at least one of the redundant electrical connectors is bonded only to the conductive member.

19. The semiconductor die assembly of claim 17 wherein each of the conductive members includes a conductive pillar that projects toward the second conductive trace.

20. The semiconductor die assembly of claim 17 wherein the conductive bond material includes metal solder.

Assignees

• Micron Technology Inc

Inventors

• Chandolu Anilkumar

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title