Interconnect structure with redundant electrical connectors and associated systems and methods

US9356009B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9356009-B2
Application numberUS-201414287418-A
CountryUS
Kind codeB2
Filing dateMay 27, 2014
Priority dateMay 27, 2014
Publication dateMay 31, 2016
Grant dateMay 31, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

First claim

Opening claim text (preview).

I claim: 1. A semiconductor die assembly, comprising: a first semiconductor die; a second semiconductor die; and an interconnect structure coupling the first semiconductor die to the second semiconductor die, wherein the interconnect structure is between the first and second semiconductor dies, and wherein the interconnect structure includes— a first conductive film coupled to the first semiconductor die, a second conductive film coupled to the second semiconductor die, and a plurality of redundant electrical connectors extending between and attached to the first and second conductive films, wherein all of the redundant electrical connectors are electrically coupled to one another via the first conductive film. 2. The semiconductor die assembly of claim 1 wherein the interconnect structure further includes another redundant electrical connector that is attached to the first conductive film and separated from the second conductive film. 3. The semiconductor die assembly of claim 1 wherein the redundant electrical connectors each include: a conductive member coupled to the first conductive film; and a solder material coupled to the conductive member, wherein the interconnect structure further includes (1) another redundant electrical connector having a conductive member and (2) a solder material that fails to electrically connect the conductive member of the other redundant electrical connector with the second conductive film. 4. The semiconductor die assembly of claim 1 wherein: the first semiconductor die includes a first substrate and a first through-substrate via (TSV) extending through the first substrate, wherein the first TSV is coupled to the first conductive film; and the second semiconductor die includes a second substrate and a second TSV extending through the second substrate, wherein the second TSV is coupled to the second conductive film. 5. The semiconductor die assembly of claim 1 wherein: the first semiconductor die includes a substrate and a through-substrate via (TSV) extending through the substrate, wherein the TSV is coupled to the first conductive film; and at least one of the redundant electrical connectors extends between the TSV and the second conductive film. 6. The semiconductor die assembly of claim 1 wherein each of the first and second conductive films includes a conductive trace. 7. The semiconductor die assembly of claim 1 wherein: the first semiconductor die is a logic die or a memory die; and the second semiconductor die is a logic die or a memory die. 8. A semiconductor die assembly, comprising: a first semiconductor die having a first conductive trace; a second semiconductor die having a second conductive trace; a plurality of redundant electrical connectors extending between the first and second conductive traces, wherein each of the redundant electrical connectors includes— a conductive member coupled to the first conductive trace, wherein the conductive member includes an end portion, and a conductive bond material between the conductive member and the second conductive trace, wherein the conductive bond material is bonded to the end portion of the conductive member, wherein all of the redundant electrical connectors are coupled to the first conductive trace. 9. A semiconductor die assembly, comprising: a first semiconductor die having a first conductive trace; a second semiconductor die having a second conductive trace; a plurality of redundant electrical connectors extending between the first and second conductive traces, wherein each of the redundant electrical connectors includes— a conductive member coupled to the first conductive trace, wherein the conductive member includes an end portion; and a conductive bond material between the conductive member and the second conductive trace, wherein the conductive bond material is bonded to the end portion of the conductive member, wherein— the conductive bond material of at least one of the redundant electrical connectors is bonded only to the end portion of the conductive member, and at least another one of the redundant electrical connectors is electrically coupled to the first conductive trace. 10. The semiconductor die assembly of claim 8 wherein each of the redundant electrical connectors further includes a bond pad between the conductive bond material and the second conductive trace. 11. The semiconductor die assembly of claim 8 wherein each of the conductive members includes a conductive pillar that projects toward the second conductive trace. 12. The semiconductor die assembly of claim 8 wherein each of the conductive members includes: a raised bond coupled to the second conductive trace; and a conductive pillar coupled to the first conductive trace and projecting toward the raised bond pad. 13. The semiconductor die assembly of claim 8 wherein the conductive bond material includes metal solder. 14. The semiconductor die assembly of claim 8 wherein the first semiconductor die includes a substrate and a through-substrate via (TSV) extending through the substrate, wherein the TSV is coupled to the first conductive trace. 15. A semiconductor die assembly, comprising: a first semiconductor die having a first conductive trace; a second semiconductor die having a second conductive trace; and a plurality of redundant conductive members coupled to the first conductive trace and extending vertically toward the second semiconductor die, wherein the redundant conductive members are electrically coupled to one another via the first conductive traces, and wherein all of the redundant conductive members are coupled to the second conductive trace of the second semiconductor die. 16. The semiconductor die assembly of claim 15 wherein the redundant conductive members are spaced laterally apart from one another and configured to transfer heat between the first and second semiconductor dies. 17. The semiconductor die assembly of claim 16 , further comprising: a package substrate carrying the second semiconductor die; and a thermally conductive casing at least partially enclosing the first and second semiconductor dies within an enclosure. 18. The semiconductor die assembly of claim 15 , further comprising: another conductive member coupled to the first conductive trace, the conductive member having an end portion separated from the first and second conductive traces; and metal solder attached only to the end portion of the other redundant conductive member.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between stacked chips · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

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What does patent US9356009B2 cover?
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first se…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).