Interconnect structure with redundant electrical connectors and associated systems and methods

Patent metadata

Field	Value
Publication number	US-10192852-B2
Application number	US-201715724102-A
Country	US
Kind code	B2
Filing date	Oct 3, 2017
Priority date	May 27, 2014
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

First claim

I claim:

1. A semiconductor device, comprising:
a semiconductor substrate;
a dielectric material over the substrate;
a conductive trace extending at least partially through the dielectric material; and
a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—
a conductive member coupled to the conductive trace, and
a conductive bond material bonded to the conductive member,

wherein all of the redundant electrical connectors are coupled to the conductive trace.

2. The semiconductor device of claim 1 wherein the dielectric includes a plurality of openings exposing portions of the conductive trace, wherein the redundant electrical connectors are formed in the openings.

3. The semiconductor device of claim 1 wherein the conductive member comprises copper and the bond material comprises a solder material.

4. The semiconductor device of claim 1 wherein the conductive member includes an end portion, and wherein the conductive bond material and conductive member form a conductive joint at the end portion.

5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate, wherein the TSV is electrically coupled to the conductive trace and each of the redundant electrical connectors.

6. The semiconductor device of claim 5 wherein the redundant electrical connectors extend away from the conductive trace in a first direction and the TSV extends away from the conductive trace in a second direction generally opposite the first direction.

7. The semiconductor device of claim 5 , further comprising a substrate contact on a portion of the conductive trace and positioned directly between the conductive trace and TSV.

8. The semiconductor device of claim 5 wherein the conductive trace is a first conductive trace, and the substrate includes a first side proximate the first conductive trace and a second side opposite the first side, wherein the TSV extends from the first side to the second side, the semiconductor device further comprising:
a second conductive trace electrically coupled to the TSV; and
a plurality of conductive bond pads, wherein all of the bond pads are coupled to one another via the second conductive trace.

9. The semiconductor device of claim 1 wherein the conductive member includes generally vertical sidewalls and a barrier and/or seed material covering at least a portion of the sidewalls.

10. A semiconductor device, comprising:
a semiconductor die;
a conductive film over and electrically coupled to the semiconductor die;
a dielectric material over the semiconductor die and at least partially covering the conductive film, wherein a plurality of openings extend at least partially through the dielectric material to the conductive film; and
a plurality of redundant electrical connectors directly on the conductive film, wherein each of the redundant electrical connectors extends through portions of the dielectric film and is positioned within the openings, and wherein each of the redundant electrical connectors is electrically coupled to each of the other redundant electrical connectors via the conductive film.

11. The semiconductor device of claim 10 wherein each of the redundant electrical connectors includes—
a conductive pillar having an end portion, wherein the conductive pillar is directly attached to the conductive film; and
a conductive bond material bonded to the end portion of the conductive pillar.

12. The semiconductor device of claim 10 wherein each of the redundant electrical connectors includes a raised bond directly on the conductive film and extending away from the semiconductor die.

13. The semiconductor device of claim 10 wherein the conductive film is a conductive trance and the semiconductor die is a logic die or a memory die.

14. The semiconductor device of claim 10 wherein the semiconductor die includes a first side proximate the conductive film and a second side opposite the first side, the semiconductor device further comprising a through-substrate via (TSV) extending from the first side to the second side, wherein the TSV is electrically coupled to each of the redundant electrical connectors.

15. The semiconductor device of claim 14 wherein the conductive film is a first conductive film, the semiconductor device further comprising:
a second conductive film at the second side of the semiconductor die; and
a plurality of raised bonds on the second conductive film, wherein each of the raised bonds is electrically coupled to each of the other raised bonds via the second conductive film.

16. The semiconductor device of claim 15 wherein the redundant electrical connectors on the first conductive film extend away from the semiconductor die in a first direction and the raised bonds on the second conductive film extend away from the semiconductor die in a second direction generally opposite the first direction.

17. The semiconductor device of claim 14 , further comprising a conductive bond pad on the conductive film and positioned between the TSV and the conductive film.

Assignees

• Micron Technology Inc

Inventors

• Chandolu Anilkumar

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title