Shielding using layers with staggered trenches

Patent metadata

Field	Value
Publication number	US-11626366-B2
Application number	US-202117360793-A
Country	US
Kind code	B2
Filing date	Jun 28, 2021
Priority date	Jun 22, 2021
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.

First claim

What is claimed is:

1. An integrated circuit comprising:
a bottom conductive plate of a capacitor above a substrate;
a top conductive plate of the capacitor above the bottom conductive plate;
an intermetal dielectric layer formed between the bottom conductive plate and the top conductive plate, the intermetal dielectric layer being formed of at least a first dielectric material;
a plurality of shield layers disposed between the top conductive plate and a portion of the intermetal dielectric layer; and
wherein a first shield layer of the plurality of shield layers has a shield dielectric layer formed of at least a second dielectric material having a higher dielectric constant than the first dielectric material and the first shield layer includes a first trench extending through the first shield layer but not through a second shield layer of the plurality of shield layers.

2. The integrated circuit as recited in claim 1 wherein at least one of the plurality of shield layers includes a charge distribution layer in addition to the shield dielectric layer.

3. The integrated circuit as recited in claim 2 wherein the charge distribution layer is formed by silicon rich oxide (SRO).

4. The integrated circuit as recited in claim 2 wherein at least one of the plurality of shield layers does not include a charge distribution layer.

5. The integrated circuit as recited in claim 1 wherein the shield dielectric layer is formed by one or more of silicon nitride and silicon oxynitride.

6. The integrated circuit as recited in claim 1 wherein the second shield layer of the plurality of shield layers includes a second trench extending through the second shield layer and not the first shield layer and the second shield layer includes the second dielectric material.

7. The integrated circuit as recited in claim 6 wherein the first trench and the second trench are separated by an overlap region formed by portions of the first shield layer and the second shield layer.

8. The integrated circuit as recited in claim 1 wherein an additional layer of the first dielectric material is sandwiched between at least two of the plurality of shield layers.

9. The integrated circuit as recited in claim 1 further comprising at least two trenches in at least one of the plurality of shield layers.

10. The integrated circuit as recited in claim 1 wherein the first trench has a width that is based on a height of the capacitor.

11. The integrated circuit as recited in claim 1 further comprising:
a third shield layer of the plurality of shield layers below the second shield layer and above at least a portion of the intermetal dielectric layer; and
a third trench formed in the third shield layer, the third trench extending through the third shield layer and not extending through the first shield layer or the second shield layer.

12. The integrated circuit as recited in claim 1 further comprising a bond wire attached to a top surface of the top conductive plate.

13. An integrated circuit comprising:
a bottom conductive plate of a capacitor above a substrate;
a top conductive plate of the capacitor;
a passivation layer is disposed above the top conductive plate;
an intermetal dielectric layer is disposed above the bottom conductive plate and below the top conductive plate and formed of a first dielectric material;
a first shield layer is disposed under the top conductive plate and above the intermetal dielectric layer, the first shield layer including a first dielectric layer formed of at least a second dielectric material, the second dielectric material having a higher dielectric constant than the first dielectric material, the first shield layer further including a first charge distribution layer;
wherein the first shield layer has a first trench to block a horizontal current path through the first shield layer;
a second shield layer underneath the first shield layer, the second shield layer including a second dielectric layer formed of at least the second dielectric material, the second shield layer further including a second charge distribution layer;
wherein the second shield layer has a second trench to block another horizontal current path through the second shield layer; and
wherein the first trench and the second trench are horizontally offset and are separated by an overlap region formed by a portion of the first shield layer and another portion of the second shield layer.

Assignees

• Silicon Lab Inc

Inventors

• Fowler Thomas C
• Wenske Jerome T

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W29/01

  Manufacture or treatment · CPC title

• H10W29/00

  Generic parts of integrated devices, not otherwise provided for · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title