Integrated contact silicide with tunable work functions

Patent metadata

Field	Value
Publication number	US-11626288-B2
Application number	US-202117389772-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Jul 30, 2021
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.

First claim

The invention claimed is:

1. A method for reducing interface resistance between an Epi surface and a contact material, comprising:
selectively depositing a metal silicide layer on the Epi surface at a deposition temperature of approximately 150 degrees Celsius or less, wherein the metal silicide layer is deposited by selectively depositing a metal from a metal precursor and silicon from a silicon precursor to form the metal silicide layer on the Epi surface; and
adjusting a metal-to-silicon ratio of the metal silicide layer during deposition of the metal silicide layer to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than or equal to approximately 0.3 eV for the P type Epi surface or the N type Epi surface.

2. The method of claim 1 , wherein the metal silicide layer is a molybdenum silicide-based material or a ruthenium silicide-based material.

3. The method of claim 1 , wherein the work function for the P type Epi surface is adjusted to a value of approximately 5.0 eV.

4. The method of claim 1 , wherein the work function for the N type Epi surface is adjusted to a value of approximately 3.8 eV.

5. The method of claim 1 , further comprising:
depositing the metal silicide layer using atomic layer deposition.

6. The method of claim 1 , further comprising:
further adjusting the metal-to-silicon ratio by depositing on the metal silicide layer a metal or silicon using atomic layer deposition, ion implantation, or plasma vapor deposition.

7. The method of claim 1 , wherein the P type Epi surface is a silicon germanium material with or without a silicon cap layer or the N type Epi surface is a silicon phosphide material with or without a molybdenum cap layer.

8. The method of claim 1 , further comprising:
selectively depositing the metal silicide layer on the Epi surface prior to deposition of a contact etch stop layer; and
adjusting the metal-to-silicon ratio of the metal silicide layer during deposition prior to deposition of the contact etch stop layer.

9. The method of claim 8 , further comprising:
performing an activation anneal after adjusting the metal-to-silicon ratio.

10. The method of claim 8 , further comprising:
performing an activation anneal prior to selectively depositing the metal silicide layer.

11. The method of claim 8 , further comprising:
depositing the contact etch stop layer as a conformal nitride-based etch stop layer on a substrate;
depositing a dielectric layer on the substrate;
opening a contact on the substrate; and
depositing a bulk fill material onto the contact.

12. A method for reducing interface resistance between an Epi surface and a contact material, comprising:
selectively depositing a molybdenum silicide layer on the Epi surface using atomic layer deposition at a deposition temperature of approximately 120 degrees Celsius or less, wherein the Epi surface has upper surfaces and undercut surfaces and wherein the molybdenum silicide layer is deposited by selectively depositing molybdenum from a molybdenum precursor and silicon from a silicon precursor onto the upper surfaces and the undercut surfaces of the Epi surface; and
adjusting a metal-to-silicon ratio of the molybdenum silicide layer during deposition to alter a work function of the molybdenum silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than or equal to approximately 0.3 eV for the P type Epi surface or the N type Epi surface.

13. The method of claim 12 , wherein the work function for the P type Epi surface is adjusted to a value of approximately 5.0 eV or the work function for the N type Epi surface is adjusted to a value of approximately 3.8 eV.

14. The method of claim 12 , further comprising:
further adjusting the metal-to-silicon ratio by depositing a molybdenum or silicon on the molybdenum silicide layer using atomic layer deposition, ion implantation, or plasma vapor deposition.

15. The method of claim 12 , wherein the P type Epi surface is a silicon germanium material with or without a silicon cap layer or the N type Epi surface is a silicon phosphide material with or without a molybdenum cap layer.

16. The method of claim 12 , further comprising:
selectively depositing the molybdenum silicide layer on the Epi surface prior to deposition of a contact etch stop layer; and
adjusting the metal-to-silicon ratio of the molybdenum silicide layer prior to deposition of the contact etch stop layer.

17. The method of claim 16 , further comprising:
performing an activation anneal after adjusting the metal-to-silicon ratio or prior to selectively depositing the molybdenum silicide layer.

18. A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for reducing interface resistance between an Epi surface and a contact material on a substrate to be performed, the method comprising:
selectively depositing a metal silicide layer on the Epi surface at a deposition temperature of approximately 150 degrees Celsius or less, wherein the metal silicide layer is deposited by selectively depositing a metal from a metal precursor and silicon from a silicon precursor to form the metal silicide layer on the Epi surface; and
adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than or equal to approximately 0.3 eV for the P type Epi surface or the N type Epi surface.

19. The non-transitory, computer readable medium of claim 18 , the method further comprising:
depositing the metal silicide layer using atomic layer deposition; and
adjusting the metal-to-silicon ratio by depositing on the metal silicide layer a metal or silicon using atomic layer deposition, ion implantation, or plasma vapor deposition, wherein the work function for the P type Epi surface is adjusted to a value of approximately 5.0 eV or wherein the work function for the N type Epi surface is adjusted to a value of approximately 3.8 eV.

20. The non-transitory, computer readable medium of claim 18 , the method further comprising:
selectively depositing the metal silicide layer on the Epi surface prior to deposition of a contact etch stop layer; and
performing an activation anneal after adjusting the metal-to-silicon ratio.

Assignees

• Applied Materials Inc

Inventors

• Hung Raymond
• Naik Mehul
• Haverty Michael

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10D64/0121 Primary

  to Group IV semiconductors · CPC title

• H10D64/62 Primary

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title