Automation methods for 3D integrated circuits and devices

Patent metadata

Field	Value
Publication number	US-11615228-B1
Application number	US-202218090134-A
Country	US
Kind code	B1
Filing date	Dec 28, 2022
Priority date	Apr 15, 2013
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing connections placement data of the second level, where the connections include planned connections between the first level and the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the connections placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

First claim

We claim:

1. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level;
providing connections placement data of said second level,
wherein said connections comprise planned connections between said first level and said second level;

performing a placement of said first level using a placer executed by a computer,
wherein said placement of said first level is based on said connections placement data,
wherein said placer is part of a Computer Aided Design (CAD) tool, and
wherein said first level comprises first routing layers; and

performing a routing of said first level by routing layers using a router executed by a computer,
wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

2. The method according to claim 1 ,
wherein a majority area of said second level comprises memory.

3. The method according to claim 1 ,
wherein results of said second level is a generic structure.

4. The method according to claim 1 ,
wherein said first level is designed to be processed with a different process node than the process node used for said second level.

5. The method according to claim 1 ,
wherein said connections are located in a top layer of said second level, and
wherein said connections are available for connection to said first level.

6. The method according to claim 1 ,
wherein said first level comprises Input and Output cells (“IO”).

7. The method according to claim 1 ,
wherein said second level comprises one or more RF (Radio Frequency) circuits.

8. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level;
providing connections placement data of said second level,
wherein said connections comprise planned connections between said first level and said second level;

performing a placement of said first level using a placer executed by a computer,
wherein said placement of said first level is based on said connections placement data,
wherein said placer is part of a Computer Aided Design (CAD) tool, and
wherein said first level comprises first routing layers; and

performing a routing of said first level by routing layers using a router executed by a computer,
wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool, and
wherein a majority area of said second level comprises memory circuits.

9. The method according to claim 8 ,
wherein a majority area of said first level comprises logic circuits.

10. The method according to claim 8 ,
wherein results of said second level is a generic structure.

11. The method according to claim 8 ,
wherein said first level is designed to be processed with a different process node than the process node used for said second level.

12. The method according to claim 8 ,
wherein said connections are located in a top layer of said second level, and
wherein said connections are available for connection to said first level.

13. The method according to claim 8 ,
wherein said first level comprises Input and Output cells (“IO”).

14. The method according to claim 8 ,
wherein said second level comprises one or more RF (Radio Frequency) circuits.

15. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level;
providing connections placement data of said second level,
wherein said connections comprise planned connections between said first level and said second level;

performing a placement of said first level using a placer executed by a computer,
wherein said placement of said first level is based on said connections placement data,
wherein said placer is part of a Computer Aided Design (CAD) tool, and
wherein said first level comprises first routing layers; and

performing a routing of said first level routing layers using a router executed by a computer,
wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool, and
wherein a majority area of said second level comprises non-logic circuits such as memory circuits or Radio Frequency (“RF”) circuits or analog circuits.

16. The method according to claim 15 ,
wherein a majority area of said first level comprises logic circuits.

17. The method according to claim 15 ,
wherein results of said second level is a generic structure.

18. The method according to claim 15 ,
wherein said first level is designed to be processed with a different process node than the process node used for said second level.

19. The method according to claim 15 ,
wherein said connections are located in a top layer of said second level, and
wherein said connections are available for connection to said first level.

20. The method according to claim 15 ,
wherein said first level comprises Input and Output cells (“IO”).

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Wurman Zeev

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title