Automation for monolithic 3D devices

Patent metadata

Field	Value
Publication number	US-11487928-B2
Application number	US-202217841619-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Apr 15, 2013
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A method of designing 3D Integrated Circuits including: partitioning at least one design into at least two levels, a first and second level, where the first level includes logic, the second level includes memory; and then receiving a first placement of at least portion of the second level, where the first placement includes a placement of a first memory array, where the Circuit includes a plurality of connections between the first level and second level; performing a second placement of the first level based on the first placement, the performing a second placement includes using a placer computer executed, where the placer is a part of a Computer Aided Design tool, where the logic includes a first logic circuit configured to write data to the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.

First claim

We claim:

1. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first and a second level,
wherein said first level comprises logic and said second level comprises memory; and then

receiving a first placement of at least portion of said second level,
wherein said first placement comprises a placement of a first memory array,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and

performing a second placement of said first level based on said first placement,
wherein said performing a second placement comprises using a placer executed by a computer,
wherein said placer is a part of a Computer Aided Design (CAD) tool,
wherein said logic comprises a first logic circuit configured so as to write data to said first memory array, and
wherein performing said second placement comprises placing said first logic circuit based on said first placement of said first memory array.

2. The method according to claim 1 ,
wherein said first level comprises first routing layers,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said first routing layers.

3. The method according to claim 1 ,
wherein said first logic circuit comprises at least one decoder or at least one decoder representation.

4. The method according to claim 1 ,
wherein said second level comprises a plurality of memory arrays.

5. The method according to claim 1 , further comprising:
performing a third placement comprising placement of said plurality of connections.

6. A 3D Integrated Circuit made according to the method of claim 1 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form the integrated circuit.

7. The method according to claim 1 , further comprising:
performing a third placement comprising placement of said plurality of connections,
wherein said third placement is based on said first placement.

8. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first and a second level,
wherein said first level comprises logic and said second level comprises memory,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and then

receiving a first placement of at least portion of said plurality of connections,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and

performing a second placement of said first level based on said first placement,
wherein said performing a second placement comprises using a placer executed by a computer,
wherein said placer is a part of a Computer Aided Design (CAD) tool; and

performing a third placement of said second level based on said first placement,
wherein said third placement comprises a placement of a first memory array,
wherein said logic comprises a first logic circuit configured so as to write data to said first memory array.

9. The method according to claim 8 ,
wherein said first logic circuit comprises at least one decoder or at least one decoder representation.

10. The method according to claim 8 ,
wherein said second level comprises a plurality of memory arrays.

11. The method according to claim 8 ,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said second routing layers.

12. A 3D Integrated Circuit made according to the method of claim 8 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form the integrated circuit.

13. The method according to claim 8 ,
wherein said first level comprises first routing layers,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said first routing layers.

14. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first and a second level,
wherein said first level comprises logic and said second level comprises memory; and then

receiving a first placement of at least portion of said second level,
wherein said first placement comprises a placement of a first memory array and a second memory array,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and

performing a second placement of said first level based on said first placement,
wherein said performing a second placement comprise using a placer executed by a computer,
wherein said placer is a part of a Computer Aided Design (CAD) tool,
wherein said logic comprises a first logic circuit configured so as to write data to said first memory array, and
wherein performing said second placement comprises placing said first logic circuit based on said first placement of said first memory array.

15. The method according to claim 14 ,
wherein said first level comprises first routing layers,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said first routing layers.

16. The method according to claim 14 ,
wherein said first logic circuit comprises at least one decoder or at least one decoder representation.

17. The method according to claim 14 ,
wherein said second level comprises at least three independent memory arrays.

18. The method according to claim 14 , and further comprising:
a third placement comprising placement of said plurality of connections.

19. A 3D Integrated Circuit made according to the method of claim 14 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form the integrated circuit.

20. The method according to claim 14 , further comprising:
a third placement comprising placement of said plurality of connections,
wherein said third placement is based on said first placement.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Wurman Zeev

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title