Automation for monolithic 3D devices

Patent metadata

Field	Value
Publication number	US-11514221-B2
Application number	US-202217712850-A
Country	US
Kind code	B2
Filing date	Apr 4, 2022
Priority date	Apr 15, 2013
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least a first and a second level, where the first level includes logic and the second level includes memory; then performing a first placement of the second level using a placer executed by a computer, the placer is a part of a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the first level and the second level; and performing a second placement of the first level based on the first placement, where memory includes a first memory array, the logic includes a first logic circuit configured so as to write data to first memory array. Performing the first placement includes placing the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.

First claim

We claim:

1. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first and a second level,
wherein said first level comprises logic and said second level comprises memory; then

performing a first placement of said second level using a placer executed by a computer,
wherein said placer is a part of a Computer Aided Design (CAD) tool,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and

performing a second placement of said first level based on said first placement,
wherein said memory comprises a first memory array,
wherein said logic comprises a first logic circuit configured so as to write data to said first memory array,
wherein performing said first placement comprises placing said first memory array, and
wherein performing said second placement comprises placing said first logic circuit based on said first placement of said first memory array.

2. The method according to claim 1 ,
wherein said first level comprises first routing layers,
wherein said second level comprises second routing layers, and said method further comprises:

performing routing for said first routing layers and for said second routing layers.

3. The method according to claim 1 ,
wherein said first logic circuit comprises at least one decoder or at least one decoder representation.

4. The method according to claim 1 ,
wherein said memory comprises a second memory array,
wherein said first memory array comprises a first memory decoder,
wherein said second memory array comprises a second memory decoder,
wherein said placer is configured so said second memory decoder is placed outside of a rectangle, and
wherein said rectangle is at least partially defined by placement of said first memory decoder.

5. The method according to claim 1 ,
wherein said first logic circuit comprises at least one decoder representation,
wherein said decoder representation is placed on said first level,
wherein an actual memory decoder and associated bit cells are placed on said second level, and
wherein placement of said decoder representation is determined from said first memory array placement.

6. A 3D Integrated Circuit made according to the method of claim 1 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form the integrated circuit.

7. A method of designing a 3D Integrated Circuit, the method comprising:
providing at least a first level and a second level;
providing contact placement data of said first level;
performing a placement of said second level using a placer executed by a computer,
wherein said placement of said second level is based on said contact placement data,
wherein said placer is part of a Computer Aided Design (CAD) tool, and
wherein said second level comprises first routing layers; and

performing a routing of said second level routing layers using a router executed by said computer,
wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

8. The method according to claim 7 ,
wherein a majority area of said first level comprises memory.

9. The method according to claim 7 ,
wherein results of said first level is a generic platform.

10. The method according to claim 7 ,
wherein said first level is designed to be processed with a different process than how said second level is processed.

11. The method according to claim 7 ,
wherein said contacts are located in a top layer of said first level, and
wherein said contacts are available for connection to said second level.

12. The method according to claim 7 ,
wherein said contacts are located in a top layer of said first level.

13. The method according to claim 7 ,
wherein said first level comprises Input and Output cells (“IO”).

14. The method according to claim 7 ,
wherein said first level comprises one or more RF (Radio Frequency) circuits.

15. A method of designing a 3D Integrated Circuit, the method comprising:
providing a device design, and a library comprising first library cells and second library cells;
performing a synthesis step utilizing said library,
wherein said performing a synthesis step comprises execution by a computer or by another computer,
wherein said synthesis step results in a first netlist comprising first library cells and a second netlist comprising second library cells; then

performing a first placement of said first netlist on a first level using a placer; and
performing a second placement of said second netlist on a second level using the placer,
wherein said placer is executed by said computer or by another computer.

16. The method according to claim 15 ,
wherein said second placement is based on said first placement.

17. The method according to claim 15 ,
wherein said first library cells correspond to a first manufacturing process,
wherein said second library cells correspond to a second manufacturing process, and
wherein said first manufacturing process is different from said second manufacturing process.

18. The method according to claim 15 ,
wherein said first library cells correspond to a first manufacturing process,
wherein said second library cells correspond to a second manufacturing process, and
wherein said first manufacturing process is a more advanced process node than said second manufacturing process.

19. The method according to claim 15 ,
wherein said first library cells comprise low power cells, and
wherein said second library cells comprise high speed cells.

20. The method according to claim 15 ,
wherein said placer is a part of a Computer Aided Design (CAD) tool used for designing two-dimensional semiconductor devices.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Wurman Zeev

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title