Automation for monolithic 3D devices

Patent metadata

Field	Value
Publication number	US-11030371-B2
Application number	US-201816149517-A
Country	US
Kind code	B2
Filing date	Oct 2, 2018
Priority date	Apr 15, 2013
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata including logic and a memory strata including memory; then performing a first placement of the logic strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the memory strata based on the first placement, where the logic includes at least one decoder representation for the memory, where the at least one decoder representation has a virtual size with width of contacts for the through silicon vias, and where the performing a first placement includes using the decoder representation instead of an actual memory decoder.

First claim

We claim:

1. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then
performing a first placement of said logic strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices;
wherein said 3D Integrated Circuit comprises through silicon vias for connection between said logic strata and said memory strata; and

performing a second placement of said memory strata based on said first placement,
wherein said logic comprises at least one decoder representation for said memory,
wherein said at least one decoder representation has a virtual size with width of contacts for said through silicon vias, and
wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder.

2. The method according to claim 1 ,
wherein said logic strata comprises first routing layers,
wherein said memory strata comprises second routing layers, and said method further comprising:
performing routing for said first routing layers and said second routing layers.

3. The method according to claim 1 ,
wherein said performing placement comprises placement of said at least one decoder representation for at least a portion of said memory.

4. The method according to claim 1 ,
wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises first memory decoder representations and
wherein said second memory comprises second memory decoder representations, and
wherein said 2D placer is set so said second memory decoder representations are not placed within a rectangle defined by placement of said first memory decoder representations.

5. The method according to claim 1 ,
wherein said decoder representation is placed on said logic strata, and
wherein an actual memory decoder and associated bit cells are placed on said memory strata, and
wherein placement of said actual memory decoder and associated bit cells is based on said decoder representation placement.

6. The method according to claim 1 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.

7. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then
performing a first placement of said logic strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and

performing a second placement of said memory strata based on said first placement,
wherein said logic comprises at least one decoder for said memory, and
wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises first memory decoders and said second memory comprises second memory decoders,
wherein said 2D placer is set so said second memory decoders are not placed within a rectangle defined by the placement of said first memory decoders.

8. The method according to claim 7 ,
wherein a majority of said memory strata comprises memory bit cells.

9. The method according to claim 7 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.

10. The method according to claim 7 ,
wherein performing a second placement comprises the use of said 2D placer.

11. The method according to claim 7 ,
wherein said at least one decoder has a virtual size with width of contacts for through silicon vias, and
wherein said performing a first placement comprises using a decoder representation of said decoder.

12. The method according to claim 7 ,
wherein said logic strata comprises first routing layers,
wherein said memory strata comprises second routing layers, and said method further comprising:
performing routing for said first routing layers and said second routing layers.

13. The method according to claim 7 , further comprising:
performing a synthesis step utilizing at least two libraries.

14. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then
performing a first placement of said logic strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and

performing a second placement of said memory strata based on said first placement,
wherein said partitioning comprises a step of assigning at least one memory block to said logic strata for improved balancing of said logic strata area and said memory strata area.

15. The method according to claim 14 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.

16. The method according to claim 14 ,
wherein said logic strata comprises first routing layers,
wherein said memory strata comprises second routing layers, and said method further comprising:
performing routing for said first routing layers and said second routing layers.

17. The method according to claim 14 ,
wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises first memory decoder representations and said second memory comprises second memory decoder representations, and
wherein said 2D placer is set so said second memory decoder representations are not placed within a rectangle defined by the placement of said first memory decoder representations.

18. The method according to claim 14 ,
wherein said performing placement comprises placement of said at least one decoder representation for at least a portion of said memory, and
wherein placement of said at least a portion of said memory is defined by the placement of said at least one decoder representation.

19. The method according to claim 14 ,
wherein said at least one decoder representation has a virtual size with width of contacts for through silicon vias, and
wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder.

20. The method according to claim 14 ,
wherein said logic comprises at least one decoder for said memory.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Wurman Zeev

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title