Multitier arrangements of integrated devices, and methods of forming sense/access lines

Patent metadata

Field	Value
Publication number	US-11600666-B2
Application number	US-202117170488-A
Country	US
Kind code	B2
Filing date	Feb 8, 2021
Priority date	May 1, 2019
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.

First claim

We claim:

1. A method of forming an arrangement, comprising:
forming an assembly comprising, along a cross-section, a first set of memory cells on one side of a coupling region, and a second set of memory cells on an opposing side of the coupling region; an intervening insulative material being within the coupling region; the memory cells of the first and second sets being over a first series of sense/access lines;
forming a conductive interconnect within the coupling region and extending through the intervening insulative material;
forming a first conductive material to extend across the memory cells of the first and second sets, and across the conductive interconnect; the first conductive material directly contacting upper surfaces of the memory cells and an upper surface of the conductive interconnect;
removing the first conductive material from over the upper surface of the conductive interconnect, while leaving remaining portions of the first conductive material over the memory cells of the first and second sets; and
forming a second conductive material over the remaining portions of the first conductive material and over the upper surface of the conductive interconnect, and patterning the first and second conductive materials into a sense/access line of a second series.

2. The method of claim 1 wherein the removing of the first conductive material utilizes a polishing process.

3. The method of claim 1 wherein:
the cross-section is along a plane; and
the conductive interconnect is one of many substantially identical conductive interconnects, with others of the conductive interconnects being formed out of the plane of the cross-section.

4. The method of claim 3 wherein the sense/access line of the second series is one of many sense/access lines of the second series, with others of the sense/access lines of the second series being formed out of the plane of the cross-section.

5. The method of claim 4 wherein the sense/access lines of the first series are wordlines, and wherein the sense/access lines of the second series are bitlines.

6. The method of claim 1 wherein the memory cells of the first and second sets are self-selecting memory cells comprising chalcogenide.

7. The method of claim 6 wherein the memory cells of the first and second sets include upper and lower electrodes, and wherein the chalcogenide is between the upper electrodes and the lower electrodes.

8. The method of claim 1 wherein each of the memory cells of the first and second sets includes a programmable material and a select device.

9. The method of claim 8 wherein the memory cells of the first and second sets include upper electrodes, lower electrodes and middle electrodes between the upper and lower electrodes; a first ovonic material being between the upper electrodes and the middle electrodes, and a second ovonic material being between the middle electrodes and the lower electrodes; one of the first and second ovonic materials being the programmable material of the memory cells, and the other of the first and second ovonic materials being incorporated into ovonic threshold switches of the select devices.

10. The method of claim 1 wherein the memory cells of first and second sets are within one tier of a multitier configuration; and wherein the conductive interconnect is coupled with circuitry in another tier of the multitier configuration, with said other tier being vertically offset from said one tier.

11. The method of claim 10 wherein said other tier is below said one tier, and wherein the circuitry in said other tier includes CMOS circuitry.

12. The method of claim 1 wherein the first conductive material has a higher resistance than the second conductive material.

13. The method of claim 1 wherein the first conductive material comprises one or more of carbon, WSiN, WN and TiN, where the chemical formulas indicate constituents rather than specific stoichiometries; and wherein the second conductive material comprises one or more of Ta, Pt, Cu, W and Pd.

14. The method of claim 1 wherein the first and second conductive materials comprise metal.

15. The method of claim 1 wherein the first conductive material comprises a first metal in combination with one or more non-metallic elements, and wherein the second conductive material consists of a second metal.

16. The method of claim 15 wherein the first and second metals are the same.

17. The method of claim 16 wherein the first conductive material consists of WSiN, where the chemical formula indicates constituents rather than a specific stoichiometry; and wherein the second conductive material consists of W.

18. The method of claim 15 wherein the first and second metals are different.

Assignees

• Micron Technology Inc

Inventors

• Wei Lei
• Li Hongqi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10B63/24 Primary

  of the Ovonic threshold switching type · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title