Cross-point memory and methods for fabrication of same

Patent metadata

Field	Value
Publication number	US-11600665-B2
Application number	US-202017069347-A
Country	US
Kind code	B2
Filing date	Oct 13, 2020
Priority date	Feb 25, 2014
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate;
a lower conductive line above the substrate and extending in a first direction;
an upper conductive line above the lower conductive line and extending in a second direction different than the first direction; and
a memory cell stack between the lower conductive line and the upper conductive line, the memory cell stack comprising:
a storage element; and
a lateral plateau region between the storage element and the lower conductive line, wherein:
all portions of the memory cell stack between the lateral plateau region and the upper conductive line are less wide than the lateral plateau region;
all portions of the memory cell stack between the lateral plateau region and the lower conductive line are at least as wide as the lateral plateau region; and

the lateral plateau region is wider than the storage element in the first direction and in the second direction.

2. The memory device of claim 1 , wherein:
the lateral plateau region has a first width;
the storage element has a second width that is smaller than the first width; and
the second width is at least as wide as all portions of the memory cell stack between the storage element and the upper conductive line.

3. The memory device of claim 1 , further comprising:
an electrode between the storage element and the lower conductive line, wherein an upper surface of the electrode comprises the lateral plateau region; and
a dielectric material, wherein:
a first portion of the dielectric material extends from the lower conductive line to the upper conductive line and is in contact with a first sidewall of the electrode, wherein a thickness of the first portion of the dielectric material is smaller than a separation between the memory cell stack and a second memory cell stack; and
a second portion of the dielectric material extends from the lower conductive line to the upper conductive line and is in contact with a second sidewall of the electrode, wherein a thickness of the second portion of the dielectric material is smaller than a separation between the memory cell stack and a third memory cell stack.

4. The memory device of claim 3 , wherein:
the first portion of the dielectric material is in contact with the upper surface of the electrode; and
the second portion of the dielectric material is in contact with the upper surface of the electrode.

5. The memory device of claim 3 , further comprising:
a first protective liner between the first portion of the dielectric material and a first sidewall of the storage element, wherein the first protective liner extends from the upper surface of the electrode to the upper conductive line; and
a second protective liner between the second portion of the dielectric material and a second sidewall of the storage element, wherein the second protective liner extends from the upper surface of the electrode to the upper conductive line.

6. The memory device of claim 5 , wherein:
the memory cell stack comprises a second electrode above the storage element;
the first protective liner is in contact with the upper surface of the electrode, the first sidewall of the storage element, and a first sidewall of the second electrode; and
the second protective liner is in contact with the upper surface of the electrode, the second sidewall of the storage element, and a second sidewall of the second electrode.

7. The memory device of claim 5 , wherein:
the first protective liner is thicker at the upper surface of the electrode than at the upper conductive line; and
the second protective liner is thicker at the upper surface of the electrode than at the upper conductive line.

8. The memory device of claim 3 , wherein:
the first portion of the dielectric material is separated from the second portion of the dielectric material by a first distance at the lower conductive line; and
the first portion of the dielectric material is separated from the second portion of the dielectric material by a second distance at the upper conductive line, the second distance smaller than the first distance.

9. The memory device of claim 3 , wherein:
the first portion of the dielectric material is conformal with the first sidewall of the electrode and the upper surface of the electrode; and
the second portion of the dielectric material is conformal with the second sidewall of the electrode and the upper surface of the electrode.

10. The memory device of claim 1 , wherein the storage element comprises a chalcogenide material.

11. A memory device, comprising:
a substrate;
a lower conductive line disposed above the substrate and extending in a first direction;
an upper conductive line disposed above the lower conductive line and extending in a second direction different than the first direction; and
a memory cell stack interposed between the lower conductive line and the upper conductive line, wherein the memory cell stack includes a lateral plateau region in the first direction such that a first width of the memory cell stack below the lateral plateau region is wider than a second width of the memory cell stack above the lateral plateau region, and wherein the lateral plateau region is wider than a storage element in the first direction and in the second direction.

12. The memory device of claim 11 , wherein the first width of the memory cell stack below the lateral plateau region is between 10% and 50% wider than the second width of the memory cell stack above the lateral plateau region.

13. The memory device of claim 11 , wherein the memory cell stack comprises an active element, and wherein the lateral plateau region is between the active element and the lower conductive line.

14. The memory device of claim 13 , wherein the memory cell stack further comprises:
an upper electrode between the active element and the upper conductive line; and
a lower electrode between the active element and the lower conductive line.

15. The memory device of claim 14 , wherein the lateral plateau region comprises a surface of the lower electrode.

16. The memory device of claim 13 , wherein the memory cell stack further comprises:
a second active element below the active element, and wherein the lateral plateau region is between the second active element and the lower conductive line.

17. The memory device of claim 16 , wherein the memory cell stack further comprises:
a second lateral plateau region between the active element and the second active element.

18. A memory device, comprising:
a lower conductive line extending in a first direction;
an upper conductive line above the lower conductive line and extending in a second direction different than the first direction;
a memory cell stack between the lower conductive line and the upper conductive line, the memory cell stack comprising a lower electrode, a storage element, an upper electrode, wherein a surface of the lower electrode comprises a lateral plateau region, and wherein the lateral plateau region is wider than the storage element in the first direction and in the second direction;
a first protective liner in contact with the lateral plateau region, a first sidewall of the storage element, and a first sidewall of the upper electrode; and
a second protective liner in contact with the lateral plateau region, a second sidewall of the storage element that opposes the first sidewall of the storage element, and a second sidewall of the upper electrode that opposes the first sidewall of the upper electrode.

19. The memory device of

Assignees

• Micron Technology Inc

Inventors

• Ravasio Marcello
• Sciarrillo Samuele
• Pellizzer Fabio
• Tortorelli Innocenzo
• Somaschini Roberto
• Casellato Cristina
• Mottadelli Riccardo

Classifications

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10B63/24 Primary

  of the Ovonic threshold switching type · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/801

  Constructional details of multistable switching devices · CPC title