Floating gate memory cell and memory array structure

Patent metadata

Field	Value
Publication number	US-11600628-B2
Application number	US-202016743070-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Jan 15, 2020
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.

First claim

What is claimed is:

1. A method of manufacturing a floating gate memory cell, comprising:
forming a memory device on a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer, wherein forming the memory device comprises:
forming a control gate in the semiconductor layer of the SOI substrate;
forming an insulating layer on the control gate; and
forming a floating gate on the insulating layer; and

forming a transistor device on the SOI substrate, wherein an active region of the transistor device is formed in the bulk semiconductor layer of the SOI substrate.

2. The method according to claim 1 , wherein the insulating layer comprises an oxide-nitride-oxide (ONO) layer.

3. The method according to claim 1 , further comprising:
forming a read/write gate of the transistor device; and
electrically connecting the floating gate of the memory device to the read/write gate of the transistor device.

4. The method according to claim 3 , wherein electrically connecting the floating gate of the memory device to the read/write gate of the transistor device further comprises:
forming a contact in a metallization layer; and
electrically connecting an electrode on the floating gate of the memory device and an electrode on the read/write gate of the transistor device via the contact in the metallization layer.

5. A floating gate memory cell, comprising:
a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer;
a memory device, comprising:
a control gate formed in the semiconductor layer of the SOI substrate;
an insulating layer formed on the control gate; and
a floating gate formed on the insulating layer; and

a transistor device electrically connected to the memory device, wherein an active region of the transistor device is formed in the bulk semiconductor layer of the SOT substrate.

6. The floating gate memory cell according to claim 5 , further comprising an erase electrode for erasing the memory device, wherein the erase electrode may be formed in the semiconductor layer or as a separate electrode.

7. The floating gate memory cell according to claim 5 , wherein the transistor device further comprises:
a gate dielectric layer formed on the bulk semiconductor layer of the SOI substrate; and
a read/write gate formed on the gate dielectric layer.

8. The floating gate memory cell according to claim 7 , further comprising an electrical connection between the floating gate of the memory device and the read/write gate of the transistor device.

9. The floating gate memory cell according to claim 8 , wherein the electrical connection comprises:
a metal contact formed in a metallization layer;
an electrode formed on the floating gate of the memory device;
an electrode formed on the read/write gate of the transistor device;
a contact formed on the floating gate electrode and electrically contacting the metal contact in the metallization layer; and
a contact formed on the read/write and electrically contacting the metal contact in the metallization layer.

10. A memory array, comprising:
a plurality of floating gate memory cells, each floating gate memory cell comprising:
a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer;
a memory device, comprising:
a control gate formed in the semiconductor layer of the SOI substrate;
an insulating layer formed on the control gate; and
a floating gate formed on the insulating layer; and

an active area electrically connected to the memory device, wherein the active area is formed in the bulk semiconductor layer of the SOI substrate,
wherein each floating gate memory cell further comprises a gate electrically connecting the control gate of the memory device to the active area.

11. The memory array according to claim 10 , wherein the gate electrically connecting the control gate of the memory device to the active area comprises an L-shaped gate or a straight gate.

12. The memory array according to claim 10 , wherein each floating gate memory cell further comprises a wordline/control contact connected to the control gate, and a sourceline contact and bitline contact connected to the active area.

13. The memory array according to claim 12 , wherein a set of the floating gate memory cells share the same wordline/control contact.

14. The memory array according to claim 12 , wherein adjacent floating gate memory cells share the same sourceline contact or the same bitline contact.

Assignees

• Globalfoundries Us Inc

Inventors

• Melde Thomas

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title