Salicided structure to integrate a flash memory device with a high k, metal gate logic device

Patent metadata

Field	Value
Publication number	US-2016013197-A1
Application number	US-201414330120-A
Country	US
Kind code	A1
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates. A silicide contact pad is arranged over a top surface of the first memory cell gate. The silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate and the metal gate. A method of manufacturing the integrated circuit is also provided.

First claim

What is claimed is:

1 . An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
a semiconductor substrate including a memory region and a logic region adjacent to the memory region; a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9; a flash memory cell device arranged over the memory region, wherein the flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates; and a silicide contact pad arranged over a top surface of the first memory cell gate, wherein the silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate and the metal gate.

2 . The integrated circuit according to claim 1 , wherein the first memory cell gate is a memory gate, the second memory cell gate is a select gate, and the dielectric region includes a charge trapping dielectric arranged under the memory gate.

3 . The integrated circuit according to claim 1 , wherein the first memory cell gate is a word line or an erase gate, and the second memory cell gate is a control gate arranged over a floating gate.

4 . The integrated circuit according to claim 1 , wherein the flash memory cell device includes:
a floating gate; an erase gate and a word line spaced from the floating gate on opposite sides of the floating gate; a control gate arranged over the floating gate; and a floating gate spacer arranged between neighboring sidewalls of the control gate, the word line, and the erase gate; wherein the first memory cell gate is the word line or the erase gate, the second memory cell gate is the control gate, and the dielectric region includes the floating gate spacer.

5 . The integrated circuit according to claim 1 , further including:
a first interlayer dielectric substructure arranged over the silicide contact pad, wherein a top surface of the first interlayer dielectric substructure is coplanar with top surfaces of the metal gate and the second memory cell gate.

6 . The integrated circuit according to claim 5 , further including:
a contact etch stop arranged over the silicide contact pad between the first interlayer dielectric substructure and the silicide contact pad.

7 . The integrated circuit according to claim 5 , further including:
a second interlayer dielectric substructure independent of the first interlayer dielectric substructure and arranged over the first interlayer dielectric substructure, wherein a bottom surface of the second interlayer dielectric substructure is coplanar with top surfaces of the metal gate and the second memory cell gate, and wherein the first and second interlayer dielectric substructures collectively cover the logic and memory regions.

8 . The integrated circuit according to claim 1 , further including:
a conductive contact extending vertically down to the silicide contact pad.

9 . The integrated circuit according to claim 1 , wherein the memory cell gate includes a spacer arranged over another top surface of the first memory cell gate.

10 . A method for manufacturing an embedded flash memory device, said method comprising:
forming a memory cell device over a memory region of a semiconductor substrate, the memory cell device including a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates; forming a logic device over a logic region of the semiconductor substrate, the logic device having a sacrificial gate separated from the semiconductor substrate by a material with a dielectric constant exceeding 3.9; recessing a top surface of the first memory cell gate relative to top surfaces of the dielectric region, the second memory cell gate and the sacrificial gate; forming a silicide contact pad over the recessed top surface of the first memory cell gate; and replacing the sacrificial gate with a metal gate.

11 . The method according to claim 10 , further including:
forming a bottom anti-reflective coating around the memory cell device; etching back the memory cell device; and performing an etch selective of the first memory cell gate to recess the top surface of the first memory cell gate.

12 . The method according to claim 10 , further including:
subsequent to forming the silicide contact pad, forming a first interlayer dielectric layer over the memory and logic regions; and performing a planarization into the first interlayer dielectric layer to a top surface of the second memory cell gate and to above the top surface of the first memory cell gate.

13 . The method according to claim 12 , further including:
forming a contact etch stop layer between the silicide contact pad and the first interlayer dielectric layer; and performing the planarization through portions of the contact etch stop layer.

14 . The method according to claim 12 , further including:
subsequent to replacing the sacrificial gate with the metal gate, forming a second interlayer dielectric layer over top surfaces of the first interlayer dielectric and the logic and memory regions.

15 . The method according to claim 10 , wherein the replacing includes:
removing the sacrificial gate to form a recess; forming a metal gate layer filling the recess; and performing a planarization into the metal gate layer to form the metal gate with the top surface of the metal gate coplanar with the second memory cell gate.

16 . The method according to claim 10 , further including:
forming a conductive contact extending vertically down to the silicide contact pad.

17 . The method according to claim 10 , further including:
forming the memory cell device with a spacer arranged over another top surface of the first memory cell gate.

18 . The method according to claim 10 , further including:
forming the memory cell device by at least:
forming a select gate;
forming a memory gate spaced from the select gate; and
forming a charge trapping dielectric arranged under the memory gate and between neighboring sidewalls of the select and memory gate;
wherein the first memory cell gate is the memory gate, the second memory cell gate is the select gate, and the dielectric region includes the charge trapping dielectric.

19 . The method according to claim 10 , further including:
forming the memory cell device by at least:
forming a control gate arranged over a floating gate;
forming a floating gate spacer over sidewalls of the control gate; and
forming an erase gate and a word line spaced from the floating gate on opposite sides of the floating with the floating gate spacer arranged between neighboring sidewalls of the control gate, the word line, and the erase gate;
wherein the first memory cell gate is the erase gate or the word line, the second memory cell gate is the control gate, and the dielectric region includes the floating gate spacer.

20 . An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
a semiconductor substrate including a memory region and a logic region adjacent to the memory region, the memory region including a common source/drain region and a pair of individual source/drain regions arranged on opposite sides of the common source/drain region; a logic device arranged over the logic re

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Ming Chyi

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/696 Primary

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title