Integrated circuits with flash memory and methods for producing the same

Patent metadata

Field	Value
Publication number	US-9780231-B1
Application number	US-201615271528-A
Country	US
Kind code	B1
Filing date	Sep 21, 2016
Priority date	Sep 21, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a handle layer. A partial buried insulator overlies the handle layer and underlies the active layer, terminates at a buried insulator termination point, and includes an electrically insulating material. A substrate extension is adjacent to the partial buried insulator, where the substrate extension overlies the handle layer and underlies the active layer, and where the substrate extension directly contacts the partial buried insulator at the buried insulator termination point. The substrate extension includes a semiconductive material. A memory gate overlies the active layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate comprising an active layer and a handle layer, wherein the active layer overlies the handle layer;
a partial buried insulator overlying the handle layer and underlying the active layer, wherein the partial buried insulator terminates at a buried insulator termination point, and wherein the partial buried insulator comprises an electrically insulating material;
a substrate extension adjacent to the partial buried insulator, wherein the substrate extension overlies the handle layer and underlies the active layer, wherein the substrate extension comprises a semiconductive material, and wherein the substrate extension directly contacts the partial buried insulator at the buried insulator termination point; and
a memory gate overlying the active layer.

2. The integrated circuit of claim 1 wherein a portion of the memory gate directly overlies the partial buried insulator and another portion of the memory gate directly overlies the substrate extension.

3. The integrated circuit of claim 1 further comprising:
a first isolation structure extending through the active layer and into the handle layer; and
a second isolation structure extending through the active layer and into the handle layer, wherein a memory area is defined between the first isolation structure and the second isolation structure, and wherein the partial buried insulator and the substrate extension are positioned in the memory area.

4. The integrated circuit of claim 3 further comprising:
a well contact positioned outside of the memory area.

5. The integrated circuit of claim 4 further comprising:
a third isolation structure extending through the active layer and into the handle layer, wherein a well contact area is defined between the third isolation structure and the second isolation structure, and wherein the well contact is positioned within the well contact area.

6. The integrated circuit of claim 5 wherein the well contact overlies the active layer within the well contact area.

7. The integrated circuit of claim 3 further comprising:
a source;
a drain, wherein the memory gate is positioned between the source and the drain, and wherein the source and the drain overlie the active layer within the memory area.

8. The integrated circuit of claim 3 wherein the partial buried insulator directly contacts the first isolation structure and the substrate extension directly contacts the second isolation structure.

9. The integrated circuit of claim 3 further comprising:
a first well defined within the handle layer, wherein the first well has a first well concentration of conductivity determining impurities; and wherein
the active layer within the memory area has an active layer concentration of conductivity determining impurities that is less than the first well concentration of conductivity determining impurities.

10. The integrated circuit of claim 9 further comprising a deep well defined within the handle layer, wherein the first well overlies the deep well, wherein the first well comprises one of P or N type conductivity determining impurities and the deep well comprises the other of P or N type conductivity determining impurities.

11. The integrated circuit of claim 9 wherein the first well concentration comprises a gradient.

12. The integrated circuit of claim 1 further comprising:
a source overlying the active layer; and
a drain overlying the active layer, wherein the memory gate is between the source and the drain.

13. The integrated circuit of claim 1 wherein the memory gate comprises:
a tunnel dielectric overlying the active layer; and
a floating gate overlying the tunnel dielectric.

14. The integrated circuit of claim 13 wherein the memory gate comprises:
a gate dielectric overlying the floating gate; and
a control gate overlying the gate dielectric.

15. An integrated circuit comprising:
a substrate comprising an active layer, a partial buried insulator, and a handle layer, wherein the active layer overlies the partial buried insulator, and the partial buried insulator overlies the handle layer;
a first isolation structure passing through the active layer and into the handle layer;
a second isolation structure passing through the active layer and into the handle layer, wherein a memory area is defined between the first isolation structure and the second isolation structure, and wherein the partial buried insulator is within the memory area;
a third isolation structure passing through the active layer and into the handle layer, wherein a well contact area is defined between the second isolation structure and the third isolation structure;
a memory gate overlying the active layer in the memory area; and
a well contact in electrical communication with the substrate in the well contact area, wherein the well contact is in electrical communication with the active layer within the memory area.

16. The integrated circuit of claim 15 further comprising:
a substrate extension positioned within the memory area, wherein the substrate extension underlies the active layer and overlies the handle layer, and wherein the substrate extension directly contacts the partial buried insulator.

17. The integrated circuit of claim 16 wherein a portion of the memory gate directly overlies the partial buried insulator and another portion of the memory gate directly overlies the substrate extension.

18. The integrated circuit of claim 16 further comprising:
a source overlying the active layer in the memory area, wherein the source directly overlies the partial buried insulator; and
a drain overlying the active layer in the memory area, wherein the drain directly overlies the substrate extension.

19. The integrated circuit of claim 15 wherein the well contact overlies the active layer in the well contact area.

20. A method of producing an integrated circuit comprising:
removing a portion of an active layer from a substrate;
removing a portion of a buried insulator layer from the substrate to form a partial buried insulator, wherein a remaining portion of the active layer overlies the partial buried insulator;
epitaxially growing a substrate extension adjacent to the partial buried insulator;
forming an active layer extension directly overlying the substrate extension, wherein the active layer extension forms a portion of the active layer;
forming a first isolation structure in the substrate;
forming a second isolation structure in the substrate such that the partial buried insulator and the substrate extension are positioned between the first isolation structure and the second isolation structure; and
forming a memory gate overlying the active layer between the first isolation structure and the second isolation structure.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Li Pinghui
• Zhu Ming
• Shum Danny Pak-Chum
• Cai Xinshu
• Chan Darin

Classifications

• H01L29/7881 Primary

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title