Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-11600570-B2
Application number	US-202017097337-A
Country	US
Kind code	B2
Filing date	Nov 13, 2020
Priority date	Mar 17, 2020
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first impurity region and a second impurity region, which are provided in a substrate and are spaced apart from each other, a top surface of the second impurity region being higher than a top surface of the first impurity region;
a device isolation pattern interposed between the first impurity region and the second impurity region;
a first contact plug, which directly contacts the first impurity region and has a bottom surface lower than the top surface of the second impurity region;
a gap-fill insulating pattern interposed between the first contact plug and the second impurity region;
a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region; and
a first spacer, which directly contacts a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern,
wherein the first protection spacer directly contacts the first spacer.

2. The semiconductor memory device of claim 1 ,
wherein the first protection spacer has an ‘L’ or ‘J’-shaped section.

3. The semiconductor memory device of claim 1 ,
wherein a portion of the device isolation pattern is interposed between the first protection spacer and the second impurity region.

4. The semiconductor memory device of claim 1 , further comprising:
a first conductive line, which directly contacts the first contact plug and crosses over the substrate in a first direction;
a second conductive line, which is extended in a second direction crossing the first direction and is adjacent to the first impurity region, in the substrate; and
a capping pattern, which directly contacts the second conductive line and is interposed between the second conductive line and the first conductive line,
wherein the bottom surface of the first contact plug is lower than a top surface of the capping pattern, and
wherein the first protection spacer includes a first portion interposed between an upper side surface of the capping pattern and the side surface of the first contact plug.

5. The semiconductor memory device of claim 4 , further comprising:
a polysilicon spacer interposed between the first protection spacer and the first contact plug,
wherein the polysilicon spacer comprises the same material as the first contact plug.

6. The semiconductor memory device of claim 5 , further comprising:
a first buffer layer interposed between the capping pattern and the first conductive line,
wherein a side surface of the first buffer layer is not aligned with the upper side surface of the capping pattern adjacent thereto.

7. The semiconductor memory device of claim 6 , further comprising:
a second buffer layer interposed between the first buffer layer and the first conductive line,
wherein the first protection spacer further includes a second portion that is interposed between the side surface of the first contact plug and the side surface of the first buffer layer and between the side surface of the first contact plug and a side surface of the second buffer layer.

8. The semiconductor memory device of claim 7 ,
wherein the side surface of the second buffer layer extends toward the first contact plug beyond the side surface of the first buffer layer,
wherein the first protection spacer further includes a protruding portion interposed between the top surface of the capping pattern and a bottom surface the second buffer layer, and
wherein the protruding portion of the first protection spacer directly contacts the side surface of the first buffer layer.

9. The semiconductor memory device of claim 8 , further comprising:
a third buffer layer interposed between the second buffer layer and the first conductive line,
wherein the first to third buffer layers comprises different materials from each other.

10. The semiconductor memory device of claim 9 ,
wherein the first protection spacer directly contacts the side surface of the first buffer layer, the side surface of the second buffer layer, and a side surface of the third buffer layer.

11. The semiconductor memory device of claim 1 , further comprising:
a second protection spacer, which is spaced apart from the first protection spacer with the first contact plug interposed therebetween and is interposed between the gap-fill insulating pattern and a third impurity region,
wherein the device isolation pattern is further interposed between the third impurity region and the first impurity region,
wherein the gap-fill insulating pattern is further interposed between the first contact plug and the third impurity region,
wherein the first protection spacer comprises the same material as the second protection spacer, and
wherein the first protection spacer and the second protection spacer have different shapes from each other.

12. The semiconductor memory device of claim 11 ,
wherein, when measured at the same level, a distance between the first contact plug and the first protection spacer is different from a distance between the first contact plug and the second protection spacer.

13. The semiconductor memory device of claim 1 ,
wherein the second impurity region is disposed near a portion of the first contact plug,
the semiconductor memory device further comprises:
a third impurity region, which is disposed in the substrate and near another side of the first contact plug and is spaced apart from the first and second impurity regions;
a second contact plug, which directly contacts the second impurity region and is spaced apart from the first contact plug; and
a third contact plug, which directly contacts the third impurity region and is spaced apart from the first contact plug, and
a width of the second contact plug is different from a width of the third contact plug.

14. The semiconductor memory device of claim 1 , further comprising:
a first conductive line, which directly contacts the first contact plug and crosses over the substrate in a first direction,
wherein the first conductive line comprises a metal-containing pattern, and
the first protection spacer is extended to directly contacts a bottom surface of the metal-containing pattern.

15. A semiconductor memory device, comprising:
a device isolation pattern disposed in a substrate to define a plurality of active regions;
a recess region defined in the device isolation pattern and the substrate and having a first inner side surface and a second inner side surface opposite to each other;
a first impurity region and a second impurity region disposed in a first active region of the plurality of active regions and a second active region of the plurality of active regions, respectively, the first impurity region being provided in the substrate exposed through a bottom surface of the recess region;
a bit-line contact, which directly contacts the first impurity region and is disposed in the recess region;
a first protection spacer covering a lower portion of the first inner side surface of the recess region; and
a second protection spacer covering a lower portion of the second inner side surface of the recess region,
wherein the first protection spacer and the second protection spacer comprise the same material and have different shapes from each other.

16. The semiconductor memory device of claim 15 , further comprising:
a first lower gap-fill insulating pattern disposed in the recess region and between the bit-line contact and the first protection spacer; and
a second lower gap-fill insulating pattern disposed in

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyo-Sub
• Park Sohyun
• Kim Daewon
• Kim Dongoh
• Kim Eun A
• Park Chulkwon
• Park Taejin
• Lee Kiseok
• Han Sunghee

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/46

  comprising air gaps · CPC title