Semiconductor device, module and system each including the same, and method for manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-9412642-B2
Application number	US-201514696156-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	Mar 27, 2012
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact region between each storage node contact and an active region is increased in size. The semiconductor device includes a device isolation film defining an active region, a bit line contact coupling the active region to a bit line, and a barrier formed below the bit line located between the bit line contacts.

First claim

What is claimed is:

1. A method for forming a semiconductor device comprising:
forming a device isolation film defining an active region;
forming a first interlayer insulation film over the active region and the device isolation film;
forming first and second bit line contact holes by etching the first interlayer insulation film;
forming a trench in the first interlayer insulation film connecting the first and second bit line contact holes;
forming a barrier in the trench;
forming first and second bit line contacts in the first and second bit line contact holes, respectively; and
forming a bit line over the bit line contact and the barrier.

2. The method according to claim 1 , further comprising:
when forming the barrier, simultaneously forming a contact spacer over a sidewall of the bit line contact hole.

3. The method according to claim 1 , further comprising:
forming first and second storage node contacts coupled to first and second ends of the active region, respectively.

4. The method according to claim 3 , wherein forming the first and second storage node contacts includes:
forming a second interlayer insulation film over the bit line and the first interlayer insulation film;
forming storage node contact holes by etching the second interlayer insulation film and the first interlayer insulation film to expose the first and the second end of the active region in a first etching process;
increasing widths of lower parts of the storage node contact holes by etching lower parts of the storage node contact holes in a second etching process after the first etching process; and
forming a storage node contact material in the storage node contact holes.

5. The method according to claim 1 , wherein forming the trench includes:
etching the interlayer insulation film to expose the device isolation film.

Assignees

• Sk Hynix Inc

Inventors

• Chung In Seung

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10W15/01

  Manufacture or treatment · CPC title