Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells

Patent metadata

Field	Value
Publication number	US-11600494-B2
Application number	US-202117318470-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Sep 11, 2018
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

First claim

The invention claimed is:

1. A method used in forming an array of elevationally-extending strings of memory cells, comprising:
forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the stack comprising an etch-stop tier between a first tier and a second tier of the stack, the etch-stop tier being of different composition from those of the insulative tiers and the wordline tiers;
etching into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier;
penetrating through the etch-stop tier to extend individual of the channel openings there-through;
after extending the individual channel openings through the etch-stop tier, etching into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier; and
forming transistor channel material in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier;
providing the wordline tiers to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells, charge-storage material between the transistor channel material and the control-gate regions, insulative charge-passage material between the transistor channel material and the charge-storage material, and a charge-blocking region between the charge-storage material and individual of the control-gate regions;
providing the control-gate material after forming the transistor channel material; and
replacing the etch-stop tier with the control-gate material after forming the transistor channel material.

2. The method of claim 1 wherein the first tier is a top tier of the stack and the second tier is a bottom tier of the stack.

3. The method of claim 1 wherein the etch-stop tier is insulative.

4. The method of claim 1 wherein the etch-stop tier comprises an oxide comprising at least one of Mg and Hf.

5. The method of claim 4 wherein the oxide comprises Mg.

6. The method of claim 4 wherein the oxide comprises Hf.

7. The method of claim 4 wherein the oxide comprises Mg and Hf.

8. The method of claim 4 wherein the oxide comprises Al.

9. The method of claim 4 wherein the oxide comprises Si.

10. The method of claim 1 wherein the etching to the etch-stop tier over-etches partially into the etch-stop tier.

11. The method of claim 10 wherein the etching to the etch-stop tier over-etches into less than half of vertical thickness of the etch-stop tier.

12. A method used in forming an array of elevationally-extending strings of memory cells, comprising:
forming upper and lower stacks individually comprising vertically-alternating insulative tiers and wordline tiers;
forming lower channel openings in the lower stack;
forming upper channel openings into the upper stack to individual of the lower channel openings to form interconnected channel openings individually comprising one of individual of the lower channel openings and one of individual of the upper channel openings;
at least one of the upper and lower stacks comprising an intra-stack etch-stop tier between a top tier and a bottom tier of the respective upper or lower stack, the intra-stack etch-stop tier being of different composition from those of the insulative tiers and the wordline tiers of the respective upper or lower stack;
the forming of at least one of all of the lower channel openings and all of the upper channel openings comprising:
etching into the insulative tiers and the wordline tiers that are above the intra-stack etch-stop tier to the intra-stack etch-stop tier to form the respective lower channel openings or the upper channel openings to have individual bases comprising the intra-stack etch-stop tier;
penetrating through the intra-stack etch-stop tier to extend individual of the respective lower channel openings or the upper channel openings there-through; and
after extending the individual channel openings through the intra-stack etch-stop tier, etching into and through the insulative tiers and the wordline tiers that are below the intra-stack etch-stop tier to extend the respective individual upper or lower channel openings deeper into the respective upper or lower stack below the intra-stack etch-stop tier; and

forming transistor channel material in the individual upper and lower channel openings elevationally along the intra-stack etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the intra-stack etch-stop tier.

13. The method of claim 12 wherein the intra-stack etch-stop tier is insulative.

14. The method of claim 12 wherein the intra-stack etch-stop tier comprises an oxide comprising at least one of Mg and Hf.

15. The method of claim 14 wherein the oxide comprises Mg.

16. The method of claim 14 wherein the oxide comprises Hf.

17. The method of claim 14 wherein the oxide comprises Mg and Hf.

18. The method of claim 14 wherein the oxide comprises Al.

19. The method of claim 14 wherein the oxide comprises Si.

20. The method of claim 12 wherein the etching to the intra-stack etch-stop tier over-etches partially into the intra-stack etch-stop tier.

21. The method of claim 20 wherein the etching to the intra-stack etch-stop tier over-etches into less than half of vertical thickness of the intra-stack etch-stop tier.

Assignees

• Micron Technology Inc

Inventors

• Hopkins John D
• Haller Gordon A
• John Tom J
• Khandekar Anish A
• Larsen Christopher
• Shrotri Kunal

Classifications

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title