Semiconductor devices and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11588012-B2
Application number	US-202117200081-A
Country	US
Kind code	B2
Filing date	Mar 12, 2021
Priority date	May 18, 2018
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate:
a lower insulating layer disposed on the substrate and including a through hole;
a contact structure disposed in the through hole of the lower insulating layer;
an upper insulating layer disposed on the lower insulating layer;
a lower electrode structure passing through the upper insulating layer and contacting the contact structure, the lower electrode structure including a first lower electrode and a second lower electrode that is disposed on the first lower electrode;
a dielectric layer disposed on the lower electrode structure; and
an upper electrode disposed on the dielectric layer,
wherein the first lower electrode of the lower electrode structure includes niobium oxide,
the second lower electrode of the lower electrode structure includes niobium nitride, and is disposed on an inner side surface and an inner bottom surface of the first lower electrode,
the dielectric layer includes hafnium oxide, and is disposed on an inner side surface and an inner bottom surface of the second lower electrode of the lower electrode structure and on an outer side surface of the first lower electrode of the lower electrode structure, and
the dielectric layer contacts a top surface of the first lower electrode of the lower electrode structure and a top surface of the second lower electrode of the lower electrode structure.

2. The semiconductor device of claim 1 , wherein the dielectric layer has a tetragonal crystalline phase.

3. The semiconductor device of claim 1 , wherein the dielectric layer contacts a top surface of the upper insulating layer.

4. The semiconductor device of claim 1 , wherein the inner side surface of the first lower electrode of the lower electrode structure contacts an outer side surface of the second lower electrode of the lower electrode structure, and
the inner bottom surface of the first lower electrode of the lower electrode structure contacts an outer bottom surface of the second lower electrode of the lower electrode structure.

5. The semiconductor device of claim 1 , wherein the top surface of the first lower electrode of the lower electrode structure is substantially coplanar with the top surface of the second lower electrode of the lower electrode structure.

6. The semiconductor device of claim 1 , wherein each of the first lower electrode of the lower electrode structure and the second lower electrode of the lower electrode structure is cylinder-shaped with an upper opened end, and
the upper electrode fills in the upper opened end of the second lower electrode of the lower electrode structure.

7. The semiconductor device of claim 1 , wherein the dielectric layer further includes at least one from among zirconium oxide, aluminum oxide, silicon oxide, titanium oxide, yttrium oxide, scandium oxide, and lanthanum oxide.

8. The semiconductor device of claim 1 , wherein the lower electrode structure includes a third lower electrode that is disposed on the outer side surface and an outer bottom surface of the first lower electrode of the lower electrode structure, and
the third lower electrode contacts a top surface of the contact structure.

9. The semiconductor device of claim 8 , wherein the third lower electrode of the lower electrode structure includes at least one selected from among doped polysilicon, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride and iridium oxide.

10. A semiconductor device comprising:
a substrate;
a lower insulating layer disposed on the substrate and including a through hole;
a contact structure disposed in the through hole of the lower insulating layer;
an upper insulating layer disposed on the lower insulating layer;
a lower electrode structure passing through the upper insulating layer and contacting the contact structure, the lower electrode structure including a first lower electrode and a second lower electrode, the first lower electrode including a bottom portion and a side portion that is disposed on the bottom portion;
a dielectric layer disposed on the lower electrode structure; and
an upper electrode disposed on the dielectric layer,
wherein the second lower electrode of the lower electrode structure is disposed on a top surface of the bottom portion of the first lower electrode, an inner side surface of the side portion of the first lower electrode, an outer side surface of the side portion of the first lower electrode and a top surface of the side portion of the first lower electrode, and
the dielectric layer is disposed on the second lower electrode of the lower electrode structure and does not contact the first lower electrode of the lower electrode structure.

11. The semiconductor device of claim 10 , wherein the first lower electrode of the lower electrode structure includes niobium oxide, the second lower electrode of the lower electrode structure includes niobium nitride, and the dielectric layer includes hafnium oxide having a tetragonal crystalline phase.

12. The semiconductor device of claim 11 , wherein the dielectric layer further includes at least one from among zirconium oxide, aluminum oxide, silicon oxide, titanium oxide, yttrium oxide, scandium oxide, and lanthanum oxide.

13. The semiconductor device of claim 10 , wherein a side surface of the bottom portion of the first lower electrode contacts the upper insulating layer.

14. The semiconductor device of claim 10 , wherein the dielectric layer contacts a top surface of the upper insulating layer.

15. The semiconductor device of claim 10 , wherein a bottom surface of the bottom portion of the first lower electrode contacts a top surface of the contact structure.

16. A semiconductor device comprising:
a substrate;
a lower insulating layer disposed on the substrate and including a through hole;
a contact structure disposed in the through hole of the lower insulating layer;
an upper insulating layer disposed on the lower insulating layer;
a lower electrode structure disposed on the upper insulating layer, and including a first lower electrode, a second lower electrode and a third lower electrode;
a supporter disposed on the upper insulating layer;
a dielectric layer disposed on the lower electrode structure; and
an upper electrode disposed on the dielectric layer,
wherein the first lower electrode of the lower electrode structure is cylinder-shaped with a filled interior,
the first lower electrode of the lower electrode structure passes through the upper insulating layer and contacts a top surface of the contact structure,
the second lower electrode of the lower electrode structure is disposed on a side surface and a top surface of the first lower electrode of the lower electrode structure,
the third lower electrode of the lower electrode structure is disposed on a side surface and a top surface of the second lower electrode of the lower electrode structure,
the dielectric layer is disposed on a side surface and a top surface of the third lower electrode of the lower electrode structure, and contacts the supporter and the upper insulating layer, and
the dielectric layer does not contact the first lower electrode and the second lower electrode of the lower electrode structure.

17. The semiconductor device of claim 16 , wherein the first lower electrode of the lower electrode structure includes at least one selected from among doped polysilicon, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride and iridium oxide,
the second lower electrode of the lower ele

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Jun-Goo
• Kang Sang-Yeol
• Kim Youn-Soo
• Lee Jin-Su
• Jung Hyung-Suk
• Cho Kyu-Ho

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title