Methods and apparatus for processing a substrate

Patent metadata

Field	Value
Publication number	US-11587799-B2
Application number	US-202016939652-A
Country	US
Kind code	B2
Filing date	Jul 27, 2020
Priority date	Dec 2, 2019
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

Methods and apparatus for processing a substrate are provided herein. For example, the method can include depositing a first layer of metal on a first substrate; depositing a second layer of metal atop the first layer of metal; depositing a third layer of metal on a second substrate; depositing a fourth layer of metal atop the third layer of metal; and bringing the second layer of material into contact with the fourth layer of material under conditions sufficient to cause the first substrate to be bonded to the second substrate by a diffusion layer formed by portions of the first layer of metal diffusing through the second layer of metal and portions of the third layer of metal diffusing through the fourth layer of metal.

First claim

The invention claimed is:

1. A method for processing a substrate comprising:
depositing a first layer of metal on a first substrate;
depositing a second layer of metal atop the first layer of metal;
depositing a third layer of metal on a second substrate;
depositing a fourth layer of metal atop the third layer of metal; and
bringing the second layer of metal into contact with the fourth layer of metal under conditions sufficient to cause the first substrate to be bonded to the second substrate by a diffusion layer formed by portions of the first layer of metal diffusing through the second layer of metal and portions of the third layer of metal diffusing through the fourth layer of metal.

2. The method of claim 1 , further comprising, prior to depositing the first layer of metal on the first substrate and the third layer of metal on the second substrate, depositing, on the first substrate and the second substrate, a layer of dielectric material including at least one of silicon oxide, silicon nitride, or silicon carbon nitride.

3. The method of claim 2 , wherein depositing the layer of dielectric material is performed using one of chemical vapor deposition or atomic layer deposition.

4. The method of claim 1 , wherein depositing the first layer of metal, the second layer of metal, the third layer of metal, and the fourth layer of metal is performed using one of physical vapor deposition, chemical vapor deposition, e-beam deposition, or electroplating, electroless deposition.

5. The method of claim 1 , further comprising:
wherein the first layer of metal and the third layer of metal are at least one of copper or nickel; and
wherein the second layer of metal and the fourth layer of metal are at least one of silver, palladium, platinum, or gold.

6. The method of claim 1 , wherein the first substrate and the second substrate are made from at least one of silicon, glass, copper, stainless steel, or aluminum.

7. The method of claim 1 , wherein the first substrate comprises a cooling module on which the first layer of metal is deposited, wherein the second substrate comprises at least one of an integrated chip or system on chip on which the third layer of metal is deposited, and wherein the method further comprises:
transferring the at least one of the integrated chip or system on chip to a carrier substrate from the second substrate prior to depositing the third layer of metal on the second substrate; and
after bonding the first substrate to the second substrate, removing the first substrate from the cooling module and the carrier substrate from the at least one of the integrated chip or system on chip.

8. The method of claim 7 , wherein removing the first substrate from the cooling module and removing the second substrate from the at least one of the integrated chip or system on chip is performed using at least one of hydrogen or stealth laser treatment, vector field mapping (VFM) substrate cleaving, chemical mechanical polishing, or etching, and
wherein removing the carrier substrate from the at least one of the integrated chip or system on chip is performed using at least one of laser and blade dicing or plasma dicing.

Assignees

• Applied Materials Inc

Inventors

• Hsiung Chien-Kang
• Wada Yuichi
• Mori Glen T

Classifications

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W40/70

  Fillings or auxiliary members in containers or in encapsulations for thermal protection or control · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W40/037 Primary

  Assembling together parts thereof · CPC title