Carrier, laminate and method of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-11576259-B2
Application number	US-201916550151-A
Country	US
Kind code	B2
Filing date	Aug 23, 2019
Priority date	Aug 24, 2018
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A carrier configured to be attached to a semiconductor substrate via a first surface comprises a continuous carbon structure defining a first surface of the carrier, and a reinforcing material constituting at least 2 vol-% of the carrier.

First claim

What is claimed is:

1. A carrier configured to be attached to a semiconductor substrate via a first surface, comprising:
a continuous carbon structure defining the first surface of the carrier, wherein the continuous carbon structure is made of carbon; and
a reinforcing material, different than the continuous carbon structure, constituting at least 2 vol-% of the carrier,
wherein the continuous carbon structure comprises:
a carbon layer defining the first surface of the carrier;
a first trench extending into the carbon layer from a second surface of the carrier opposite to the first surface; and
a second trench extending into the carbon layer from the second surface of the carrier,

wherein a first portion of the reinforcing material fills at least part of the first trench and a second portion of the reinforcing material fills at least part of the second trench.

2. The carrier of claim 1 , wherein the reinforcing material is embedded in the continuous carbon structure.

3. The carrier of claim 1 , wherein the reinforcing material includes at least one of carbon nanotubes, graphene flakes, polycrystalline silicon, diamond, silicon nitride balls, or molybdenum balls.

4. The carrier of claim 1 , wherein the reinforcing material comprises at least one of silicon carbide, molybdenum, a matrix comprising carbon nanotubes, or a matrix comprising graphene flakes.

5. The carrier of claim 1 , wherein the reinforcing material is at least one of a reinforcing layer or a stack of reinforcing layers adjoining the continuous carbon structure.

6. The carrier of claim 1 , wherein the reinforcing material is a metal layer.

7. The carrier of claim 1 , comprising a surface protection coating on at least a second surface of the carrier opposite to the first surface.

8. The carrier of claim 7 , wherein the surface protection coating comprises at least one of nitride, polycrystalline silicon carbide, tantalum carbide (TaC), molybdenum carbide (MoC), or beryllium nitride (BN).

9. The carrier of claim 1 , wherein a thickness of the carrier is in a range between 100 μm and 2000 μm.

10. A laminate, comprising:
a carrier; and
a silicon carbide (SiC) semiconductor substrate attached on a first surface of the carrier,
wherein the carrier comprises:
a continuous carbon structure defining the first surface of the carrier, wherein the continuous carbon structure is made of carbon; and
a reinforcing material, different than the continuous carbon structure, constituting at least 2 vol-% of the carrier,

wherein the continuous carbon structure comprises:
a carbon layer defining the first surface of the carrier;
a first trench extending into the carbon layer from a second surface of the carrier opposite to the first surface; and
a second trench extending into the carbon layer from the second surface of the carrier,

wherein a first portion of the reinforcing material fills at least part of the first trench and a second portion of the reinforcing material fills at least part of the second trench.

11. The laminate of claim 10 , wherein the laminate comprises a single chip.

12. The laminate of claim 10 , wherein the SiC semiconductor substrate is a wafer comprising a plurality of chips.

13. The laminate of claim 10 , wherein the SiC semiconductor substrate comprises a power transistor.

14. The laminate of claim 10 , wherein a thickness of the SiC semiconductor substrate is in a range between 1 μm to 70 μm.

15. A method of manufacturing semiconductor devices, comprising:
attaching a semiconductor wafer on a continuous carbon structure at a first surface of a carrier;
separating the semiconductor wafer into a first part attached to the carrier and a second part detached from the carrier; and
forming semiconductor device structures, comprising at least one of a doped region or an insulating region, in the first part of the semiconductor wafer,
wherein the continuous carbon structure comprises:
a carbon layer defining the first surface of the carrier;
a first trench extending into the carbon layer from a second surface of the carrier opposite to the first surface; and
a second trench extending into the carbon layer from the second surface of the carrier,

wherein a first portion of the reinforcing material fills at least part of the first trench and a second portion of the reinforcing material fills at least part of the second trench.

16. The method of claim 15 , wherein separating the semiconductor wafer comprises:
implanting ions into the semiconductor wafer to form a splitting region in the semiconductor wafer, wherein an absorption coefficient in the splitting region is at least 5 times higher than an absorption coefficient in a region of the semiconductor wafer outside the splitting region; and
irradiating the semiconductor wafer with laser radiation.

17. The method of claim 15 , comprising, after separating the semiconductor wafer and before forming semiconductor device structures:
forming a semiconductor layer on the first part of the semiconductor wafer.

18. The method of claim 17 , comprising:
forming trenches in the semiconductor layer; and
filling the trenches with a passivation material.

Assignees

• Infineon Technologies Ag

Inventors

• Schulze Hans-Joachim
• Brockmeier Andre
• Hoechbauer Tobias Franz Wolfgang
• Metzger-Brueckl Gerhard
• Piccin Matteo
• Santos Rodriguez Francisco Javier

Classifications

• H10P10/126

  characterised by the composition of the bonding layer, e.g. dopant concentration or stoichiometry · CPC title

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title