Method for forming a semiconductor device and a semiconductor device

Patent metadata

Field	Value
Publication number	US-9704750-B2
Application number	US-201615224099-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Jul 31, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method of forming a semiconductor device and a semiconductor device are provided. The method includes providing a wafer stack including a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material and having a first side and a second side opposite the first side, the second side being attached to the carrier wafer, defining device regions of the wafer stack, partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; and further processing the device wafer while the device wafer remains supported by the residual of the carrier wafer.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
providing a wafer stack comprising a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material, the device wafer having a first side and a second side opposite the first side, the second side being attached to the carrier wafer;
defining device regions of the wafer stack;
partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; and
further processing the device wafer while the device wafer remains supported by the residual of the carrier wafer.

2. The method of claim 1 , further comprising at least one of:
forming front-side metallizations on the first side in the device regions so that the front-side metallizations are separated from each other;
forming a back-side metallization in at least one of the device regions comprising filling the openings in the carrier wafer with a conductive material; and
removing the residual of the carrier wafer after forming the back-side metallization.

3. The method of claim 2 , wherein further processing comprises at least one of:
temporarily contacting the front-side metallization in the at least one of the device regions;
temporarily contacting the back-side metallization; and
testing a functionality of the at least one of the device regions.

4. The method of claim 2 , prior to forming the front-side metallizations further comprising at least one of:
etching trenches from the first side into the device wafer;
insulating sidewalls of the trenches; and
etching a wide trench into the device wafer outside the device regions.

5. The method of claim 1 , wherein further processing comprises thermal annealing.

6. The method of claim 1 , wherein partly removing the carrier wafer is performed so that the openings are surrounded by the residual of the carrier wafer.

7. The method of claim 1 , wherein the wide band-gap semiconductor material is silicon carbide or gallium nitride.

8. The method of claim 1 , wherein providing the wafer stack comprises at least one of:
attaching a donor wafer comprising silicon carbide to a carrier wafer comprising graphite;
splitting the donor wafer along an internal delamination layer so that a split layer comprising silicon carbide and attached to the carrier wafer is formed;
epitaxially depositing silicon carbide to form a further silicon carbide layer on the split layer; and
inhibiting the epitaxially depositing outside the device regions.

9. The method of claim 8 , wherein attaching the donor wafer comprises at least one of:
depositing a ceramic-forming polymer precursor on a bonding surface of the donor wafer;
depositing the ceramic-forming polymer precursor on the carrier wafer;
forming a stack comprising the carrier wafer, the donor wafer and a bonding layer comprising the ceramic-forming polymer precursor, and arranged between the carrier wafer and the donor wafer; and
tempering the stack to form the wafer stack.

10. The method of claim 9 , wherein the ceramic-forming polymer precursor comprises a polycarbosilane.

11. The method of claim 9 , wherein the tempering takes place in an atmosphere comprising nitrogen, argon and/or hydrogen.

12. The method of claim 1 , further comprising singulating the wafer stack into individual semiconductor chips.

13. The method of claim 12 , wherein singulating the wafer stack comprises at least one of:
attaching the device wafer supported by the residual to a foil;
plasma etching the residual along scribe lines prior to attaching the device wafer to the foil;
etching from the first side at least close to the residual;
sawing from the first side at least close to the residual;
scribing the device wafer along scribe lines completely arranged within the residual when seen from above and subsequent breaking;
removing the device wafer in device regions overlapping with the residual of the carrier wafer when seen from above;
laser cutting; and
cutting through the residual.

14. A method for forming a semiconductor device, comprising:
providing a wafer stack comprising a graphite carrier wafer and a device wafer comprising a wide band-gap semiconductor material and having a first side and a second side opposite the first side and bonded to the carrier wafer;
defining device regions of the wafer stack;
forming openings in the carrier wafer so that areas of the second side in the device regions are uncovered and surrounded by a residual of the carrier wafer; and
filling the openings in the carrier wafer with a conductive material to form respective conductive regions electrically contacting the areas of the second side.

15. The method of claim 14 , wherein the wide band-gap semiconductor material is silicon carbide or gallium nitride.

16. The method of claim 14 , further comprising singulating the wafer stack into individual semiconductor chips.

17. The method of claim 16 , prior to singulating the wafer stack further comprising at least one of:
thermal annealing;
etching trenches and/or wide trenches from the first side into the device wafer;
insulating sidewalls of the trenches;
temporarily contacting the conductive regions; and
testing a functionality of one or more device regions.

18. A semiconductor device, comprising:
a semiconductor body having a first side and a second side opposite the first side and comprising a wide band-gap semiconductor material;
a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate; and
a back-side metallization arranged in the opening of the graphite substrate, surrounded by the graphite substrate, and electrically contacting the area of the second side.

19. The semiconductor device of claim 18 , wherein the wide band-gap semiconductor material is silicon carbide or gallium nitride.

20. The semiconductor device of claim 18 , wherein the graphite substrate surrounds the semiconductor body when seen from above, and/or wherein the semiconductor body is completely arranged within the graphite substrate when seen from above.

Assignees

• Infineon Technologies Ag

Inventors

• Rupp Roland
• Lehnert Wolfgang
• Santos Rodriguez Francisco Javier
• Schulze Hans-Joachim

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title